TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)

Amid NVIDIA’s leadership in the AI wave, demand for CoWoS (Chip-on-Wafer-on-Substrate) has tripled, driving TSMC to aggressively expand CoWoS capacity, with a corresponding surge in demand for System-in-Integrated-Circuit (SoIC) solutions.

According to a report from MoneyDJ citing industry sources, it has suggested that in addition to AMD, which has already implemented SoIC in production, Apple is conducting limited trial production. Furthermore, collaborations are underway with NVIDIA and Broadcom, indicating that SoIC is poised to become TSMC’s next advanced packaging solution following CoWoS.

TSMC’s SoIC is the industry’s first high-density 3D chip stacking technology, enabling heterogeneous integration of chips with different sizes, functionalities, and nodes using Chip on Wafer packaging. Currently, production takes place at the AP6 assembly and testing facility in Zhunan, Taiwan. It’s rumored that the planned advanced packaging facility in Chiayi, Taiwan will include not only two CoWoS plants but also an SoIC facility.

AMD is the first customer to adopt SoIC technology, with its latest MI300 chip using SoIC combined with CoWoS solution. Apple, TSMC’s primary customer, is reportedly interested in SoIC and plans to incorporate it with Hybrid molding technology for Mac products. Small-scale trials are currently underway, with mass production anticipated between 2025 and 2026. NVIDIA and Broadcom are also collaborating in this field.

As per the same report citing industry sources, the SoIC technology is still in its early stages, with monthly production capacity expected to reach around 2,000 wafers by the end of this year. There are prospects for this capacity to double this year and potentially exceed 10,000 wafers by 2027.

With support from major players like AMD, Apple, and NVIDIA, TSMC’s expansion in SoIC is viewed as confident, securing future orders for high-end chip manufacturing and advanced packaging.

Read more

• [News] TSMC Reportedly Sensing Increased Orders Again, CoWoS Production Capacity Surges
• [News] TSMC’s SoIC Demand Heats Up, Reports Suggest Significant Capacity Expansion

(Photo credit: TSMC)

According to a report from South Korean media outlet TheElec, Samsung’s Advanced Package (AVP) team has reportedly secured an advanced packaging order for NVIDIA’s AI chip, paving the way for future supply of NVIDIA’s high-bandwidth memory (HBM) chips.

The report, citing sources, reveals that Samsung Electronics’ Advanced Packaging team will provide interposer and 2.5D packaging technology for packaging NVIDIA’s AI processors. However, the HBM and GPU chips used in these NVIDIA AI processors will be supplied by others.

2.5D packaging technology enables the horizontal integration of chips like CPUs, GPUs, and HBMs on an interposer. Processors such as NVIDIA’s A100, H100, and Intel’s Gaudi all utilize this technology for packaging.

TSMC’s CoWoS advanced packaging facility utilizes 2.5D packaging technology, while Samsung Electronics employs their iCube technology, which also falls under the category of 2.5D packaging.

Over the past year, Samsung Electronics has been expanding its advanced packaging division by increasing personnel and developing its own interposer technology. They have also procured a large amount of 2.5D packaging equipment from Japanese semiconductor equipment suppliers such as Shinkawa and others.

The same report from TheElec also revealed that in the future, stacking eight HBM chips on a 12-inch wafer will require the use of 16 interposers. Therefore, Samsung Electronics is actively working to increase its silicon interposer production capacity.

Although Samsung Electronics has declined to comment on the rumors regarding NVIDIA’s packaging orders, industry speculation suggests a connection to insufficient capacity at TSMC’s CoWoS, compounded by recent earthquakes in Taiwan potentially further impacting TSMC’s CoWoS capacity. This has led to expectations of future growth in orders for Samsung Electronics’ Advanced Packaging Division.

Samsung Electronics’ plant located in Cheonan, South Korea, is where the company’s Advanced Packaging team is based. Recently, the production capacity at the Cheonan plant has reportedly been ramped up to full utilization, which is believed by industry observers to be one of the possible reasons why Samsung secured NVIDIA’s advanced packaging orders.

Previously reported by The Korea Times, Samsung Co-CEO Kye-Hyun Kyung stated that he expects the results of Samsung’s investment to come out in earnest from the second half of this year.

Kyung further noted that for a future generation of HBM chips called HBM4, likely to be released in 2025 with more customised designs, Samsung will take advantage of having memory chips, chip contract manufacturing and chip design businesses under one roof to satisfy customer needs.

TrendForce’s latest report reveals that in 2023, global foundry revenues hit US$117.47 billion, with TSMC accounting for close to 60% of the market share, while Samsung held approximately 11%.

Read more

• [News] Samsung Reportedly Commits to Advanced Packaging, Targets Over USD100 Million in Related Revenue This Year
• [News] Samsung Accelerates 3D Packaging with Hybrid Bonding Production Line in Korean Advanced Packaging Hub

(Photo credit: Samsung)

The semiconductor battleground of the Angstrom Era has commenced earlier than expected, with TSMC advancing its plant expansions in Taiwan. As per Commercial Times citing sources, TSMC is poised to increase its 2024 capital expenditure from the initial estimate of USD 28-32 billion to USD 30-34 billion, marking a hike of over 7%.

TSMC’s continuous plant expansion includes the initiation of the first 2-nanometer plant in Hsinchu’s Baoshan facility in April, the addition of another 2-nanometer plant in Kaohsiung, and the commencement of construction for two advanced packaging plants in Chiayi. Furthermore, there are market rumors speculating that TSMC plans to build two more A14 plants in Kaohsiung.

According to industry sources cited by the report, TSMC’s earnings call on April 18th will mark a significant milestone as the company transitions to the next generation of manufacturing processes. Expectations are high for surprises in capital expenditure, second-quarter operating prospects, and the nomination list for new directors.

During TSMC’s January earnings call, they disclosed a capital expenditure estimate of approximately USD 28-32 billion for this year. However, with NVIDIA’s recent unveiling of the Blackwell architecture, advanced packaging has become almost indispensable for next-generation chips. Major customers for advanced packaging, including NVIDIA, Broadcom, Marvell, and AMD, are all closely linked to AI.

Per the same report citing sources, it’s revealed by Commercial Times citing sources near TSMC’s clients that the current waiting time remains as long as six months, as capacity ramp-up continues to chase demand. It is widely expected that TSMC will increase its capital expenditure, with the lower bound potentially surpassing USD 28 billion to over USD 30 billion.

From an operational standpoint, TSMC is expected to benefit this year from the surge in demand for artificial intelligence. Analysts predict that AI clients will support TSMC’s second-quarter revenue momentum, with the potential to deliver low single-digit quarterly growth.

Per the report citing sources, the positive outlook for TSMC’s second quarter can be attributed to several factors. These include stable demand for TSMC’s 4nm and 5nm processes with support from NVIDIA’s GPUs. Additionally, it is speculated that the 3nm process will benefit from cryptocurrency clients and early orders for Apple’s AI chips, boosting capacity utilization. Furthermore, there is an upward trend in the mature 16nm and 28nm processes.

Per the industry sources cited by the report, TSMC’s CoWoS capacity is fully booked until the first half of next year. This will drive up the revenue contribution from TSMC’s 3nm process. Furthermore, the outsourcing orders for Intel CPUs this year will further boost revenue growth.

Additionally, on June 4th, TSMC will hold elections for ten directors, including six independent directors. The list of director candidates is about to be announced, attracting significant attention to the new team lineup. With the current Chairman, Mark Liu, announcing his succession, and independent director K.C. Chen planning to retire, significant changes in the TSMC board of directors’ composition are anticipated.

Read more

• [News] Three Major Giants Vying for TSMC’s 3-Nanometer Production Capacity
• [News] Blackwell Enters the Scene – A Closer Look at TSMC’s CoWoS Branch

(Photo credit: TSMC)

NVIDIA unveiled its Blackwell architecture and the touted powerhouse AI chip GB200 at GTC 2024 held in San Jose, California, on March 19th. Manufactured using TSMC’s 4-nanometer (4NP) process, it is expected to ship later this year.

According to a report from TechNews, TSMC’s CoWoS technology comes in various forms, including CoWoS-R, CoWoS-L, and CoWoS-S, each differing in cost due to variations in the interposer material. Customers can choose the appropriate technology based on their specific requirements.

CoWoS-R, for instance, integrates InFo technology, utilizing RDL wiring in the interposer to connect chips, making it suitable for high-bandwidth memory (HBM) and SoC integration.

On the other hand, CoWoS-L combines the advantages of CoWoS-S and InFO technologies, offering a cost-effective solution with the use of LSI (Local Silicon Interconnect) chips as the interposer for dense chip-to-chip connections. According to market reports, the Blackwell platform adopts CoWoS-L, as this technology is better suited for larger chiplets.

CoWoS-S, utilizing silicon as the interposer material, represents the highest cost variant and is currently the mainstream choice. Notably, NVIDIA’s H100, H200, and AMD’s MI300 chips all employ CoWoS-S.

NVIDIA’s latest Blackwell architecture features AI chips, including the B100, B200, and the GB200 with Grace CPU, all manufactured on TSMC’s 4-nanometer process. As per the industry sources cited by the report, insights suggest that production for the B100 is slated for the fourth quarter of this year, with mass production expected in the first half of next year.

Meanwhile, the B200 and GB200 are set to follow suit with mass production next year. As per a report from Tom’s Hardware, the AI computing performance of a single B200 GPU can reach 20 petaflops, whereas the previous generation H100 offered a maximum of only 4 petaflops of AI computing performance. The B200 will also be paired with 192GB of HBM3e memory, providing up to 8 TB/s of bandwidth.

TSMC’s advanced manufacturing processes and CoWoS packaging technology are expected to continue benefiting, particularly with the adoption of CoWoS-L packaging.

Read more

• [News] TSMC’s 4nm Process Powers NVIDIA’s Blackwell Architecture GPU, AI Performance Surpasses Previous Generations by Multiples
• [News] NVIDIA and AMD Clash in AI Chip Market, as TSMC Dominates Orders with Strong Momentum in Advanced Processes

(Photo credit: TSMC)