Powerchip Semiconductor Manufacturing Corporation (PSMC) held the inauguration ceremony for its new Tongluo plant on May 2nd. This investment project, totaling over NTD 300 billion  for a 12-inch fab, has completed the installation of its initial equipment and commenced trial production. According to a report from Commercial Times, it will serve as PSMC’s primary platform for advancing process technology and pursuing orders from large international clients.

Additionally, PSMC has ventured into advanced CoWoS packaging, primarily producing Silicon Interposers, with mass production expected in the second half of the year and a monthly capacity of several thousand units.

Frank Huang, Chairman of PSMC, stated that construction of the new Tongluo plant began in March 2021. Despite challenges posed by the pandemic, the plant was completed and commenced operations after a three-year period.

As of now, the investment in this 12-inch fab project has exceeded NTD 80 billion, underscoring the significant time, technology, and financial requirements for establishing new semiconductor production capacity. Fortunately, the company made swift decisions and took action to build the plant. Otherwise, with the recent international inflation driving up costs of various raw materials, the construction costs of this new plant would undoubtedly be even higher.

The land area of Powerchip Semiconductor Manufacturing Corporation’s Tongluo plant exceeds 110,000 square meters. The first phase of the newly completed plant comprises a cleanroom spanning 28,000 square meters. It is projected to house 12-inch wafer production lines for 55nm, 40nm, and 28nm nodes with a monthly capacity of 50,000 units. In the future, as the business grows, the company can still construct a second phase of the plant on the Tongluo site to continue advancing its 2x nanometer technology.

Frank Huang indicated that the first 12-inch fab in Taiwan was established by the Powerchip group. To date, they have built eight 12-inch fabs and plan to construct four more in the future. Some of these fabs will adopt the “Fab IP” technology licensing model. For example, the collaboration with Tata Group in India operates under this model.

According to a previous report from TechNews, Frank Huang believes that IP transfer will also become one of the important sources of revenue in the future. “Up to 7-8 countries have approached PSMC,” including Vietnam, Thailand, India, Saudi Arabia, France, Poland, Lithuania, and others, showing interest in investing in fabs, indicating optimism for PSMC’s future Fab IP operating model.

PSMC’s Fab IP strategy, according to the same report, leverages its long-term accumulated experience in plant construction and semiconductor manufacturing technology to assist other countries, extending from Japan and India to countries in the Middle East and Europe, in building semiconductor plants while earning royalties for technology transfers.

Looking ahead to the second half of the year, Frank Huang indicated that the current issue lies in the less-than-stellar performance of the economies of the United States and China. While the United States is showing relatively better performance in AI and technology, China’s performance is not as strong.

Huang believes that after the fourth quarter of this year, there is a chance for accelerated deployment of AI application products such as smartphones, PCs, and notebooks. With the explosive demand brought about by AI, 2025 is expected to be a very good year for the semiconductor industry, and PSMC has already seized the opportunity.

In addition, PSMC also mentioned that since last year, there has been a continuous tight supply of advanced CoWoS packaging. In response to the demands of global chip clients, the company has also ventured into CoWoS-related businesses, primarily providing the Silicon Interposer needed for advanced CoWoS packaging. Currently in the validation stage, mass production is expected to commence in the second half of the year, with an initial monthly capacity of several thousand units.

Read more

• [News] PSMC’s Frank Huang Explores Global Expansion through Fab IP, Diverging from TSMC’s Path
• [News] PSMC Assists Tata in Fab Establishment through Technology Transfer

(Photo credit: PSMC)

The demand for AI computing power is skyrocketing, with advanced packaging capacity becoming key. As per a report from Commercial Times citing industry sources, it has pointed out that TSMC is focusing on the growth potential of advanced packaging.

Southern Taiwan Science Park, Central Taiwan Science Park and Chiayi Science Park are all undergoing expansion. The Chiayi Science Park, approved this year, is set to construct two advanced packaging factories ahead of schedule. Phase one of Chiayi Science Park is scheduled to break ground this quarter, with first tool-in slated for the second half of next year. Phase two of Chiayi Science Park is expected to start construction in the second quarter of next year, with first tool-in planned for the first quarter of 2027, continuing to expand its share in the AI and HPC markets.

Advanced packaging technology achieves performance enhancement by stacking, thus increasing the density of inputs/outputs. TSMC recently unveiled numerous next-generation advanced packaging solutions, involving various new technologies and processes, including CoWoS-R and SoW.

The development of advanced packaging technology holds significant importance for the advancement of the chip industry. TSMC’s innovative solutions bring revolutionary wafer-level performance advantages, meeting the future AI demands of ultra-large-scale data centers.

Industry sources cited by the same report has stated that TSMC’s introduction of system-level wafer technology enables 12-inch wafers to accommodate a large number of chips, providing greater computational power while significantly reducing the space required in data centers.

This advancement also increases the power efficiency. Among these, the first commercially available SoW product utilizes an integrated fan-out (InFO) technology primarily for logic chips. Meanwhile, the stacked chip version employing CoWoS technology is expected to be ready by 2027.

As stacking technology advances, the size of AI chips continues to grow, with a single wafer potentially yielding fewer than ten super chips. Packaging capacity becomes crucial in this scenario. The industry sources cited in Commercial Time’s report also note that TSMC’s Longtan Advanced Packaging plant with a monthly capacity of 20,000 wafers is already at full capacity. The Zhunan AP6 plant is currently the main focus of expansion efforts, with equipment installation expected to ramp up in the fourth quarter at the  Central Taiwan Science Park facility, accelerating capacity preparation.

TSMC’s SoIC has emerged as a leading solution for 3D chip stacking. AMD is the inaugural customer for SoIC, with its MI300 utilizing SoIC paired with CoWoS.

Apple has also officially entered the generative AI battlefield. It’s noted by the sources as per the same report that Apple’s first 3D packaged SoIC product will be its ARM-based CPU for AI servers, codenamed M4 Plus or M4 Ultra, expected to debut as early as the second half of next year. The 3D packaged SoIC technology is projected to be further extended to consumer-grade MacBook M series processors by 2026.

NVIDIA, on the other hand, is reportedly set to launch the R100 in the second half of next year, utilizing chiplet and the CoWoS-L packaging architecture. It’s not until 2026 that they will officially introduce the X100 (tentative name), which adopts a 3D packaging solution incorporating SoIC and CoWoS-L.

As per a recent report from MoneyDJ citing industry sources, the SoIC technology is still in its early stages, with monthly production capacity expected to reach around 2,000 wafers by the end of this year. There are prospects for this capacity to double this year and potentially exceed 10,000 wafers by 2027.

With support from major players like AMD, Apple, and NVIDIA, TSMC’s expansion in SoIC is viewed as confident, securing future orders for high-end chip manufacturing and advanced packaging.

Read more

• [News] TSMC Reportedly Secures 4 Major Clients for SoIC, Including Apple, NVIDIA and Broadcom
• [News] TSMC Reportedly Sensing Increased Orders Again, CoWoS Production Capacity Surges

(Photo credit: TSMC)

In a bid to catch up with leading players like TSMC, the South Korean government is said to have approved a national-level initiative aimed at actively promoting the development of advanced chip packaging technologies, according to a report from South Korean media outlet TheElec.

Citing anonymous sources, the report on April 30th indicates that the feasibility of the aforementioned plan has passed the preliminary examination conducted by the Korea Institute of S&T Evaluation and Planning (KISTEP).

According to reports, the preliminary review targeted a national-level project with a value exceeding KRW 50 billion, with direct government sponsorship exceeding KRW 30 billion. Such projects rarely pass the review in one go, but the aforementioned chip packaging case is an exception.

Most of the reviewers at KISTEP have reportedly reached a consensus, recognizing the necessity of the project to catch up with leaders in advanced packaging like Taiwan’s TSMC, making South Korea a frontrunner.

As per TrendForce’s previous report, by 2027, Korea’s share in advanced process capacity is originally expected to reach 11.5%, with room for further growth.

However, the budget for the 7-year project has been reduced from the original KRW 500 billion to KRW 206.8 billion. After passing the preliminary feasibility review, the project is expected to be formally announced later this year (2024) and is scheduled to commence implementation next year.

Cited by the same report from TheElec, a source involved in the project stated that the budget cut was entirely expected, but the project’s single-pass approval is indeed noteworthy, indicating the government’s deep understanding of the importance of chip packaging.

Read more

• [News] South Korean Government Considering Cooperation with U.S. on Semiconductor Equipment Export Controls against China
• [News] Japan Makes Significant Investment in Semiconductors, Potentially Surpass South Korea Within a Decade

(Photo credit: TSMC)

NVIDIA’s upcoming next-generation high-end AI chip, the H200, is on the horizon. As per a report from Economic Daily News, currently, the mainstream high-end H100 chip has seen a decline in demand, putting an end to the previous state of supply shortages.

As per the same report, Taiwanese contract manufacturers openly acknowledge that the supply of H100 chips is indeed smoother now, primarily due to the alleviation of tight CoWoS advanced packaging capacity constraints.

Despite a significant short-term correction in the market price of H100 chips in China, Taiwan’s AI server manufacturers, such as Quanta and Inventec, are still striving to maximize shipments. This quarter, the momentum of AI server shipments is expected to see a significant boost.

From the perspective of server manufacturers, the demand and pricing of critical components are typically negotiated directly between cloud service providers (CSPs) and chip manufacturers like NVIDIA. Once the price and quantity are agreed upon, manufacturers are then commissioned to produce and ship the products.

Quanta emphasized that with the easing of tight capacity in upstream CoWoS advanced packaging, the supply of H100 chips has become smoother. Maintaining their previous stance, they anticipate that the momentum of AI server shipments will begin to show from this quarter onwards.

A previous report from tom’s hardware once emphasized that the ease of purchasing H100 GPUs has brought about some changes in the market as well. Customers now prioritize price and practicality when leasing AI computing services from cloud service providers.

Additionally, alternatives to the H100 GPU have emerged in the current market, offering comparable performance and software support. These may come at more affordable prices, potentially fostering a fairer market environment.

Mike Yang, Senior Vice President and General Manager of Quanta Cloud Technology (QCT), also mentioned recently that they expect to see a significant improvement in chip supply by June, which will subsequently boost server shipment performance in the second half of the year.

Read more

• [News] NVIDIA’s H100 AI Chip No Longer Out of Reach, Inventory Pressure Reportedly Forces Customers to Resell
• [News] CoWoS Capacity Shortage Challenges AI Chip Demand, while Taiwanese Manufacturers Expand to Seize Opportunities

(Photo credit: NVIDIA)

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)