Amid NVIDIA’s leadership in the AI wave, demand for CoWoS (Chip-on-Wafer-on-Substrate) has tripled, driving TSMC to aggressively expand CoWoS capacity, with a corresponding surge in demand for System-in-Integrated-Circuit (SoIC) solutions.

According to a report from MoneyDJ citing industry sources, it has suggested that in addition to AMD, which has already implemented SoIC in production, Apple is conducting limited trial production. Furthermore, collaborations are underway with NVIDIA and Broadcom, indicating that SoIC is poised to become TSMC’s next advanced packaging solution following CoWoS.

TSMC’s SoIC is the industry’s first high-density 3D chip stacking technology, enabling heterogeneous integration of chips with different sizes, functionalities, and nodes using Chip on Wafer packaging. Currently, production takes place at the AP6 assembly and testing facility in Zhunan, Taiwan. It’s rumored that the planned advanced packaging facility in Chiayi, Taiwan will include not only two CoWoS plants but also an SoIC facility.

AMD is the first customer to adopt SoIC technology, with its latest MI300 chip using SoIC combined with CoWoS solution. Apple, TSMC’s primary customer, is reportedly interested in SoIC and plans to incorporate it with Hybrid molding technology for Mac products. Small-scale trials are currently underway, with mass production anticipated between 2025 and 2026. NVIDIA and Broadcom are also collaborating in this field.

As per the same report citing industry sources, the SoIC technology is still in its early stages, with monthly production capacity expected to reach around 2,000 wafers by the end of this year. There are prospects for this capacity to double this year and potentially exceed 10,000 wafers by 2027.

With support from major players like AMD, Apple, and NVIDIA, TSMC’s expansion in SoIC is viewed as confident, securing future orders for high-end chip manufacturing and advanced packaging.

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• [News] TSMC Reportedly Sensing Increased Orders Again, CoWoS Production Capacity Surges
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(Photo credit: TSMC)

According to a report from South Korean media outlet TheElec, Samsung’s Advanced Package (AVP) team has reportedly secured an advanced packaging order for NVIDIA’s AI chip, paving the way for future supply of NVIDIA’s high-bandwidth memory (HBM) chips.

The report, citing sources, reveals that Samsung Electronics’ Advanced Packaging team will provide interposer and 2.5D packaging technology for packaging NVIDIA’s AI processors. However, the HBM and GPU chips used in these NVIDIA AI processors will be supplied by others.

2.5D packaging technology enables the horizontal integration of chips like CPUs, GPUs, and HBMs on an interposer. Processors such as NVIDIA’s A100, H100, and Intel’s Gaudi all utilize this technology for packaging.

TSMC’s CoWoS advanced packaging facility utilizes 2.5D packaging technology, while Samsung Electronics employs their iCube technology, which also falls under the category of 2.5D packaging.

Over the past year, Samsung Electronics has been expanding its advanced packaging division by increasing personnel and developing its own interposer technology. They have also procured a large amount of 2.5D packaging equipment from Japanese semiconductor equipment suppliers such as Shinkawa and others.

The same report from TheElec also revealed that in the future, stacking eight HBM chips on a 12-inch wafer will require the use of 16 interposers. Therefore, Samsung Electronics is actively working to increase its silicon interposer production capacity.

Although Samsung Electronics has declined to comment on the rumors regarding NVIDIA’s packaging orders, industry speculation suggests a connection to insufficient capacity at TSMC’s CoWoS, compounded by recent earthquakes in Taiwan potentially further impacting TSMC’s CoWoS capacity. This has led to expectations of future growth in orders for Samsung Electronics’ Advanced Packaging Division.

Samsung Electronics’ plant located in Cheonan, South Korea, is where the company’s Advanced Packaging team is based. Recently, the production capacity at the Cheonan plant has reportedly been ramped up to full utilization, which is believed by industry observers to be one of the possible reasons why Samsung secured NVIDIA’s advanced packaging orders.

Previously reported by The Korea Times, Samsung Co-CEO Kye-Hyun Kyung stated that he expects the results of Samsung’s investment to come out in earnest from the second half of this year.

Kyung further noted that for a future generation of HBM chips called HBM4, likely to be released in 2025 with more customised designs, Samsung will take advantage of having memory chips, chip contract manufacturing and chip design businesses under one roof to satisfy customer needs.

TrendForce’s latest report reveals that in 2023, global foundry revenues hit US$117.47 billion, with TSMC accounting for close to 60% of the market share, while Samsung held approximately 11%.

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• [News] Samsung Reportedly Commits to Advanced Packaging, Targets Over USD100 Million in Related Revenue This Year
• [News] Samsung Accelerates 3D Packaging with Hybrid Bonding Production Line in Korean Advanced Packaging Hub

(Photo credit: Samsung)

The semiconductor battleground of the Angstrom Era has commenced earlier than expected, with TSMC advancing its plant expansions in Taiwan. As per Commercial Times citing sources, TSMC is poised to increase its 2024 capital expenditure from the initial estimate of USD 28-32 billion to USD 30-34 billion, marking a hike of over 7%.

TSMC’s continuous plant expansion includes the initiation of the first 2-nanometer plant in Hsinchu’s Baoshan facility in April, the addition of another 2-nanometer plant in Kaohsiung, and the commencement of construction for two advanced packaging plants in Chiayi. Furthermore, there are market rumors speculating that TSMC plans to build two more A14 plants in Kaohsiung.

According to industry sources cited by the report, TSMC’s earnings call on April 18th will mark a significant milestone as the company transitions to the next generation of manufacturing processes. Expectations are high for surprises in capital expenditure, second-quarter operating prospects, and the nomination list for new directors.

During TSMC’s January earnings call, they disclosed a capital expenditure estimate of approximately USD 28-32 billion for this year. However, with NVIDIA’s recent unveiling of the Blackwell architecture, advanced packaging has become almost indispensable for next-generation chips. Major customers for advanced packaging, including NVIDIA, Broadcom, Marvell, and AMD, are all closely linked to AI.

Per the same report citing sources, it’s revealed by Commercial Times citing sources near TSMC’s clients that the current waiting time remains as long as six months, as capacity ramp-up continues to chase demand. It is widely expected that TSMC will increase its capital expenditure, with the lower bound potentially surpassing USD 28 billion to over USD 30 billion.

From an operational standpoint, TSMC is expected to benefit this year from the surge in demand for artificial intelligence. Analysts predict that AI clients will support TSMC’s second-quarter revenue momentum, with the potential to deliver low single-digit quarterly growth.

Per the report citing sources, the positive outlook for TSMC’s second quarter can be attributed to several factors. These include stable demand for TSMC’s 4nm and 5nm processes with support from NVIDIA’s GPUs. Additionally, it is speculated that the 3nm process will benefit from cryptocurrency clients and early orders for Apple’s AI chips, boosting capacity utilization. Furthermore, there is an upward trend in the mature 16nm and 28nm processes.

Per the industry sources cited by the report, TSMC’s CoWoS capacity is fully booked until the first half of next year. This will drive up the revenue contribution from TSMC’s 3nm process. Furthermore, the outsourcing orders for Intel CPUs this year will further boost revenue growth.

Additionally, on June 4th, TSMC will hold elections for ten directors, including six independent directors. The list of director candidates is about to be announced, attracting significant attention to the new team lineup. With the current Chairman, Mark Liu, announcing his succession, and independent director K.C. Chen planning to retire, significant changes in the TSMC board of directors’ composition are anticipated.

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• [News] Three Major Giants Vying for TSMC’s 3-Nanometer Production Capacity
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(Photo credit: TSMC)

NVIDIA unveiled its Blackwell architecture and the touted powerhouse AI chip GB200 at GTC 2024 held in San Jose, California, on March 19th. Manufactured using TSMC’s 4-nanometer (4NP) process, it is expected to ship later this year.

According to a report from TechNews, TSMC’s CoWoS technology comes in various forms, including CoWoS-R, CoWoS-L, and CoWoS-S, each differing in cost due to variations in the interposer material. Customers can choose the appropriate technology based on their specific requirements.

CoWoS-R, for instance, integrates InFo technology, utilizing RDL wiring in the interposer to connect chips, making it suitable for high-bandwidth memory (HBM) and SoC integration.

On the other hand, CoWoS-L combines the advantages of CoWoS-S and InFO technologies, offering a cost-effective solution with the use of LSI (Local Silicon Interconnect) chips as the interposer for dense chip-to-chip connections. According to market reports, the Blackwell platform adopts CoWoS-L, as this technology is better suited for larger chiplets.

CoWoS-S, utilizing silicon as the interposer material, represents the highest cost variant and is currently the mainstream choice. Notably, NVIDIA’s H100, H200, and AMD’s MI300 chips all employ CoWoS-S.

NVIDIA’s latest Blackwell architecture features AI chips, including the B100, B200, and the GB200 with Grace CPU, all manufactured on TSMC’s 4-nanometer process. As per the industry sources cited by the report, insights suggest that production for the B100 is slated for the fourth quarter of this year, with mass production expected in the first half of next year.

Meanwhile, the B200 and GB200 are set to follow suit with mass production next year. As per a report from Tom’s Hardware, the AI computing performance of a single B200 GPU can reach 20 petaflops, whereas the previous generation H100 offered a maximum of only 4 petaflops of AI computing performance. The B200 will also be paired with 192GB of HBM3e memory, providing up to 8 TB/s of bandwidth.

TSMC’s advanced manufacturing processes and CoWoS packaging technology are expected to continue benefiting, particularly with the adoption of CoWoS-L packaging.

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• [News] TSMC’s 4nm Process Powers NVIDIA’s Blackwell Architecture GPU, AI Performance Surpasses Previous Generations by Multiples
• [News] NVIDIA and AMD Clash in AI Chip Market, as TSMC Dominates Orders with Strong Momentum in Advanced Processes

(Photo credit: TSMC)

According to sources cited by Reuters,  TSMC is reportedly considering plans to establish a production line for its CoWoS technology in Japan. However, TSMC has yet to make any further decisions, and they have declined to comment on the matter.

CoWoS is an advanced packaging technology that stacks chips to enhance computing power, reduce energy consumption, and save space. Currently, TSMC’s CoWoS production capacity is entirely located in Taiwan.

With the booming development of artificial intelligence, global demand for advanced semiconductor packaging has surged, prompting chip suppliers like TSMC, Samsung, and Intel to strengthen their advanced packaging capabilities.

Previously, TSMC’s CEO, C.C. Wei, stated that the company plans to double its CoWoS output by the end of 2024 and further increase it in 2025. With TSMC recently completing the first phase of construction for its Kumamoto fab in Japan and announcing plans for the second phase, which will involve collaboration with Japanese companies SONY Semiconductor Solutions and Toyota Motor Corporation, with a total investment exceeding USD 20 billion and utilizing 6/7-nanometer advanced processes.

However, Joanne Chiao, an analyst at market research firm TrendForce, suggests that if TSMC establishes advanced packaging capacity in Japan, it may face limitations in scale. It remains unclear how much demand there is in Japan for CoWoS packaging, but most of TSMC’s CoWoS customers are currently in the United States.

Additionally, sources cited by Reuters’ report indicate that TSMC’s competitor, Intel, is also considering establishing an advanced packaging research facility in Japan to deepen ties with local chip supply chain companies.

Meanwhile, Samsung, another competitor of TSMC, is setting up advanced packaging research facilities in Yokohama, Japan, with government support. Furthermore, Samsung is in discussions with Japanese and other companies regarding material procurement, preparing to launch its packaging technology similar to that used by SK Hynix.

Regarding the development of the semiconductor industry in Japan, as mentioned in a previous report from TrendForce, Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development. Japan is strategically positioning itself to reclaim its former glory in the world of semiconductors.

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• [News] Subsidies to TSMC from Japan and China Increase Over Fivefold Annually
• [News] High Efficiency in TSMC Kumamoto Plant Construction Sets Stage for Potential Advanced Packaging Investment in Japan

(Photo credit: TSMC)