According to a report from Nikkei citing sources, memory giant Micron Technology is building a pilot production line for advanced high-bandwidth memory (HBM) in the United States and is considering producing HBM in Malaysia for the first time to capture more demand from the AI boom.

Reported on June 19, Micron is said to be expanding its HBM-related R&D facilities at its headquarters in Boise, Idaho, which include production and verification lines. Additionally, Micron is considering establishing HBM production capacity in Malaysia, where it already operates chip testing and assembly plants.

Nikkei’s report further noted that Micron’s largest HBM production facility is located in Taichung, Taiwan, where expansion efforts are also underway. Micron is said to have set a goal to triple its HBM market share to 24-26% by the end of 2025, which would bring it close to its traditional DRAM market share of approximately 23-25%.

Earlier this month, a report from a Japanese media outlet The Daily Industrial News also indicated that Micron planned to build a new DRAM plant in Hiroshima, with construction scheduled to begin in early 2026 and aiming for completion of plant buildings and first tool-in by the end of 2027.

Per industry sources cited by TechNews, Micron is expected to invest between JPY 600 to 800 billion in the new facility, located adjacent to the existing Fab15 facility. Initially, the new plant will focus on DRAM production, excluding backend packaging and testing, with a capacity emphasis on HBM products.

Micron, along with SK Hynix, has reportedly received certification from NVIDIA to produce HBM3e for the AI chip “H200.” Samsung Electronics has not yet received approval from NVIDIA; its less advanced HBM3 and HBM2e are currently primarily supplied to AMD, Google, and Amazon.

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• [News] HBM Supply Shortage Prompts Micron’s Expansion, Expected Schedule in Japan and Taiwan Revealed
• [News] Micron Slightly Raises Capital Expenditure for 2024, HBM Expected to Further Drive Revenue Growth in 2025

(Photo credit: Micron)

Samsung and SK hynix, which have been rapidly advancing in the High-Bandwidth Memory (HBM) arena, now confirm their intention to incorporate hybrid bonding in the upcoming 3D DRAM technology, according to the latest report by The Elec.

While the current technology uses micro bump to connect DRAM modules, hybrid bonding, which could stack chips vertically by using through-silicon-via (TSV), can eliminate the need for micro bumps, significantly reducing chip thickness.

According to an earlier report by The Korean Economic Daily, currently, DRAM comprises up to 62 billion cells on a substrate with densely integrated transistors on a flat plane, posing challenges such as current leakage and interference.

In contrast, 3D DRAM stacks transistors into multiple layers, which is expected to widen the gaps between them, thereby reducing leakage and interference.

Therefore, to replace the current horizontal placement, a 3D DRAM chip triples capacity per unit area by vertically stacking cells. This also differs from HBM, which vertically connects multiple DRAM chips.

During the International Memory Workshop 2024 conference held in Seoul last week, SK hynix announced its intention to implement hybrid bonding in the production of 3D DRAM. On the other hand, Samsung plans to launch 3D DRAM in 2025, according to an earlier report by The Korean Economic Daily.

Meantime, Samsung is also exploring 4F Square DRAM and plans to integrate hybrid bonding into the production process. If successful, the tech giant could reduce die surface area by 30% compared to the currently commercialized 6F2 DRAM, according to sources cited by The Elec. Samsung is said to implement the 4F2 structure in DRAM using 10nm or finer nodes.

Read more

• [News] Samsung Considers Hybrid Bonding a Must for 16-stack HBM
• [News] The Quiet Beginning of the 3D DRAM Market Share Battle

(Photo credit: SK hynix)

According to TrendForce’s latest memory spot price trend report, neither the spot price of DRAM nor that of NAND flash shows much sign of a turnaround in the short term. It is also worth noting that the Chinese government has been cracking down on smuggling activities since the end of May, putting more pressure on the spot prices of reball DRAM chips. Details are as follows:

DRAM Spot Price:

The price trend of the spot market continues to deviate from that of the contract market, showing no signs of a turnaround. Apart from module houses carrying too much inventory, channel markets for consumer products also remain weak and have yet to see the effects of the impending peak season. Furthermore, the Chinese government has been cracking down on smuggling activities in the spot market since the end of May. As a result, spot prices of reball DRAM chips continue to drop. A rebound is not expected in the short term. The average spot price of mainstream chips (i.e., DDR4 1Gx8 2666MT/s) has fallen by 2.54% from US$1.881 last week to US$1.835 this week.

NAND Flash Spot Price:

Enervated market transactions and sufficient inventory among channels have prevented a revitalization in demand from happening, despite spot suppliers’ willingness in compromising on prices. This has led to an ongoing divergence between spot and contract prices. Market participants are now on the fence regarding whether the market would exhibit demand for inventory replenishment in 3Q24. 512Gb TLC wafer spots have dropped by 0.57% this week, arriving at US$3.309.

Recently, Korean SSD controller manufacturer FADU announced a partnership with Western Digital to co-develop the next-generation enterprise SSD technology called “FDP (Flexible Data Placement).”

FDP is a standard technology proposed by the Open Compute Project (OCP) and is a newly approved NVMe specification (TP4146) initiated by companies such as Samsung, Meta, and Google. It aims to reduce write amplification while simplifying the integration of the entire software ecosystem.

According to a report from WeChat account DRAMeXchange, this technology not only enhances SSD performance but also significantly extends SSD lifespan.

By markedly reducing the phenomenon of “Write Amplification,” FDP can improve SSD write performance by 2 to 3 times and optimize data placement within SSD storage space. This phenomenon, when the recorded data volume is much larger than the actual client data volume, will greatly extend SSD lifespan, making it a highly regarded technological innovation in massive data exchange environments of large-scale data centers.

• WD and FADU Pioneer the Establishment of a New Standard for Memory Efficiency

Founded in 2015, FADU is a fabless startup primarily developing advanced NAND flash technologies to meet the explosive growth of data storage needs in hyperscale, enterprise, and cloud data centers. FADU is committed to producing high-performance SSD controllers and designing chips for data centers.

FADU aims to increase its market share in the SSD controller field to 30% by 2026. FADU’s CEO, Jihyo Lee, stated at an IPO briefing in July 2023 that global data centers used 50 million SSD controllers at that time, and the demand might double to 100 million in the next 2-3 years.

As a globally renowned memory manufacturer, Western Digital achieved revenues of USD 1.71 billion in 1Q24, a 2.4% increase from the previous quarter. However, due to a limited product line, Western Digital’s revenue in the Enterprise SSD sector for the quarter was USD 133 million, only up by 18.1% QoQ.

It’s worth noting that in 2Q24, the overall consumer market not yet recovers and the outlooks for PC and smartphone market for the year are conservative. Against this backdrop, Western Digital intends to accelerate Enterprise SSD product development to expand future growth momentum.

Western Digital is also aggressively pursuing shipments of high-capacity storage products, with plans to mass-produce 162-layer QLC SSDs. To accelerate the production of PCIe 5.0 SSDs, the company is collaborating with third-party controller manufacturers, breaking its tradition of in-house IC development. This strategic move underscores Western Digital’s efforts to expand its product range and support steady growth in enterprise SSD revenue.

For this collaboration, FADU and Western Digital predict that widespread adoption of FDP technology will not only help bring down total cost of ownership (TCO) but also establish a new standard for memory efficiency.

Amidst the AI wave, the importance of high-capacity, high-performance storage products is becoming increasingly prominent. HBM is undoubtedly the most sought-after product currently, with demand outbalancing supply and market value continuously rising. Meanwhile, new memory technologies are constantly emerging, heralding the coming of an era of 3D DRAM. Besides, SCM potential is about to be unleashed, and PCIe 6.0/7.0 is poised to be launched.

Read more

• [News] Memory Giant WD out of the Red in 1Q24 Driven by the AI Wave, 2Q24 to Keep Improving

(Photo credit: WD)

Earlier, a report from a Japanese media outlet The Daily Industrial News indicated that memory giant Micron planned to build a new DRAM plant in Hiroshima, with construction scheduled to begin in early 2026 and aiming for completion of plant buildings and first tool-in by the end of 2027.

According to industry sources cited by TechNews, Micron is expected to invest between JPY 600 to 800 billion in the new facility, located adjacent to the existing Fab15 facility. Initially, the new plant will focus on DRAM production, excluding backend packaging and testing, with a capacity emphasis on HBM products.

Micron’s new Hiroshima plant will be the first to adopt Extreme Ultraviolet (EUV) lithography equipment, producing new advanced 1-Gamma process DRAM developed in collaboration between Taiwan and Japan. Subsequently, it will also transition to the 1-Delta process, leading to a significant increase in EUV tool-ins and heightened cleanroom facilities.

As for Fab 15 in Hiroshima, it serves as a mass production site for HBM, handling front-end wafer production and Through-Silicon Via (TSV) processes, while back-end stacking and testing processes are managed by the Taichung back-end plant in Taiwan. Market reports cited by TechNews also suggest that due to expanding demand for HBM, Micron’s facilities in Taiwan will commence HBM production and TSV processes starting next year.

TrendForce points out that due to robust growth in the HBM market, lower production yields, larger chip sizes, and other factors, producing the same bit output in HBM requires approximately three times the wafer input compared to DDR5, potentially squeezing traditional DRAM capacity.

Given Micron’s need to accelerate its penetration into the HBM market, and with its 2025 production capacity already fully booked by customers, the construction of a new plant becomes imperative. Micron also plans to maintain its HBM product line market share at 20% to 25% by 2025, eyeing on increasing it to match traditional DRAM levels.

The new Hiroshima plant has also received subsidies from the Japanese government. In October last year, Japan’s Ministry of Economy, Trade and Industry announced subsidies totaling JPY 192 billion for Micron’s construction and equipment expenses. Additionally, subsidies of up to JPY 8.87 billion for production costs and JPY 25 billion for research and development costs were provided.

Read more

• [News] Micron Reportedly Set to Build New DRAM Plant in Hiroshima, Japan, Operational Expected by End of 2027
• [News] Micron Slightly Raises Capital Expenditure for 2024, HBM Expected to Further Drive Revenue Growth in 2025

(Photo credit: Micron)