On October 30, local time, Siemens announced that the company had signed an agreement to acquire Altair Engineering, a leading software provider in the industrial simulation and analytics market. This move strengthens Siemens’ position as a leading technology company and its leadership in the industrial software field.

Siemens AG stated that the combination of Altair’s capabilities in simulation, high-performance computing, data science, and artificial intelligence with Siemens Xcelerator will create the world’s most comprehensive AI-driven design and simulation product portfolio.

This transaction is expected to increase Siemens’ digital business revenue by more than 8%, adding approximately 600 million EUR to the 7.3 billion EUR digital business revenue reported in Siemens’ fiscal year 2023.

The transaction is anticipated to close in the second half of 2025. Altair, an information technology company headquartered in Troy, Michigan, USA, was listed on the Nasdaq in 2017.

Altair primarily provides software and cloud solutions in the fields of simulation and analytics, data science, artificial intelligence (AI), and high-performance computing (HPC). Its main products include HyperWorks, a simulation platform for structural analysis, fluid dynamics, and multidisciplinary optimization; SolidThinking, an innovative solution for product design supporting industrial design and engineering analysis; and Altair Smart Learning, a tool for machine learning and AI.

Originally an engineering consulting firm, Altair gradually expanded into the EDA field, adopting an acquisition strategy similar to other major players in the EDA industry. In 2017, Altair acquired Runtime Design Automation, a company providing tools for CPU, GPU, and system-on-chip (SoC) design engineers who rely on EDA tools.

In 2022, Altair announced the acquisition of Concept Engineering, a supplier of automatic schematic generation tools and electronic circuit and harness visualization platforms. In August 2024, Altair announced the acquisition of all outstanding shares of Metrics Design Automation Inc. (Metrics), further expanding its influence in the EDA sector.

In addition to Siemens’acquisition of Altair, the well-known EDA company Cadence has made successive acquisitions of Invecas and BETA CAE Systems. Notably, another EDA giant, Synopsys, acquired Ansys for as much as 35 billion USD, setting a new record in the industry and attracting wide attention.

Meanwhile, in recent years, facing the global wave of mergers and acquisitions in the EDA industry, Chinese EDA companies have been catching up. Through mergers and acquisitions, they are accelerating their growth. According to incomplete statistics, several domestic companies, including Empyrean, Semitronix, X-EPIC, Primarius, Rigoron, and S2C, have implemented acquisition strategies to expand and enrich their technology product lines, enhancing their core competitiveness and market influence.

(Photo credit: Siemens)

X-Epic, a prominent Chinese electronic design automation (EDA) start-up, is said to be reducing its workforce by up to 50%, according to a report by South China Morning Post. As chip design is an indispensable part to semiconductor manufacturing, the incident raises concerns about China’s push for technological self-reliance.

X-Epic, founded in 2020 by Wang Libin, a former engineer at US EDA leader Cadence Design Systems, has been established with the goal of creating indigenous EDA tools to challenge the dominance of US rivals. The field is traditionally governed by US giants including Cadence, Synopsys, and Mentor Graphics (now owned by Siemens).

Based on the definition by Cadence, EDA encompasses software, hardware, and essential services used in the design of chips and semiconductor devices. Historically, hardware architects sketched chip designs by hand and used isolated tools. However, alongside the rapid growth of AI, EDA has become indispensable as chip designs get complicated. The tool provides a simulated environment where circuits and designs are conceived and analyzed before being realized in the physical world.

According to the report, as of March, 2023, X-Epic employed approximately 400 people across offices in Nanjing, Beijing, Shanghai, Chengdu, and Shenzhen. However, the company began laying off up to half its employees recently across various departments, including its key research and development division.

The report further analyzes that in In August 2022, Washington first restricted China’s access to the EDA technology by prohibiting the export of gate all-around (GAA) capable EDA software, which creates challenges for Chinese chipmakers in adopting advanced processes such as the 3nm node and in developing high-performance computing or AI chips.

Citing data from the China Semiconductor Industry Association, the report notes that the value of China’s EDA market is projected to reach 18.5 billion yuan (USD 2.55 billion) next year, up from 9.3 billion yuan in 2020. As the market seems to be booming, X-Epic’s reported layoff highlights the challenges China’s EDA companies are facing.

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• New US EDA Software Ban May Affect China’s Advanced IC Design, Says TrendForce

(Photo credit: X-Epic)

One major challenge for China’s IC design industry is the lack of advanced domestic Electronic Design Automation (EDA) tools. Due to US export controls, suppliers like Cadence and Synopsys are unable to provide chip design software to China. Additionally, the absence of domestic EDA tools capable of operating on Chinese-made CPUs adds further pressure.

However, according to a report from TechNews, there are signs of change. Chinese company X-Epic has introduced the first EDA software capable of running on domestically produced processors in China, potentially breaking through existing limitations.

As per a report from Tom’s Hardware, at the Kunpeng Developer Day on April 25, 2024, X-Epic presented the latest developments in China’s domestic chip design software EDA.

This platform is compatible with Huawei’s Kunpeng server processors based on Armv8 architecture and also supports Phytium’s Phytium processors based on SPARCv9 architecture. This represents a significant advancement for China’s semiconductor design industry, enabling domestic chip designers to conduct chip design and simulation using local software only.

X-Epic stated that they provide a comprehensive suite of chip design software EDA tools covering various aspects such as digital chip verification, hardware simulation, system debugging, and cloud-based verification. Extensive adaptation and optimization have already been completed, including adaptation to compilation environments, C++/ASM compilation, cmake compilation scripts, and third-party function libraries. The focus of application lies particularly on Huawei’s Kunpeng platform.

X-Epic has indicated that, through tools like GalaxSim and GalaxFV, X-Epic achieved 2 to 3 times performance enhancements in multiple customer test cases on Huawei’s high-performance Kunpeng server clusters compared to non-optimized software. These enhanced capabilities have notably reduced simulation testing times and improved efficiency in system-level chip simulation verification. However, there is currently no information available regarding test results for Phytium’s Phytium processors.

Overall, this collaboration not only strengthens Huawei’s Kunpeng ecosystem but also provides a comprehensive chip design software EDA solution for China’s domestic semiconductor industry.

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• [Report Highlights] China’s EDA Industry Enters a Period of Consolidation amidst Rapid Growth

(Photo credit: X-Epic)

1. China’s EDA Industry into Fast Development with Efforts of Downstream Industries, Capital and Policies Propel

Within the broader context of China’s push for semiconductor self-sufficiency in recent years, the domestic EDA (Electronic Design Automation) industry in China has undergone remarkable growth. This growth has been spurred by a collaborative effort involving the Chinese government (through policies and investment funds), the expansion of the IC design sector (the growth of IC design scale and investments upstream and downstream), and private offered funds.

EDA companies in China are in rapid growth, and finance companies reached its zenith in 2021, with funding amounts consistently setting new records year after year. In 2022, EDA financing amounted to approximately 8 billion RMB, with companies like Primarius Technologies, Empyrean Technology, and Semitronix making their debut on the stock market. Over the past three years, these companies have sustained a continuous uptrend in their revenues. All in all, with support from various quarters, China’s EDA industry is now on a fast track to development.

2. Point Tools Take Center Stage for Chinese EDA Companies

Nowadays, the supply of EDA tools is largely controlled by Synopsys, Cadence, and Siemens EDA, three major players with deep technical expertise across the entire spectrum of EDA tools. While Empyrean Technology, having entered the arena early, boasts a comprehensive suite of EDA tools for analog circuit design and FPD, the majority of other Chinese EDA firms are strategically focusing on specialized point tools in simulation and verification.

These companies win customer recognition and purchases before broadening their path to other tool categories. Another strategic avenue pursued by Chinese EDA companies is the exploration of innovative opportunities in emerging fields such as AI chips, setting them apart from their larger counterparts.

3. China’s EDA Industry Enters a Phase of Consolidation, Confronting Challenges of Inexperience and Political Risks

Over the past few years, the number of Chinese EDA companies and the scale of funding have surged dramatically. As they experience rapid growth, mergers and acquisitions (M&A) and investments have become indispensable means for Chinese EDA firms to fortify their positions. This trend is becoming increasingly conspicuous, with a total of 20 M&A and investment deals occurring within the Chinese EDA sectors over the past three years, comprising 2 in 2021, 15 in 2022, and 3 in the first half of 2023.

Primarius Technologies (with 9 deals), Empyrean Technology (with 3 deals), and Univesta (with 4 deals, one of which was unsuccessful) are among the firms with comparatively high M&A activity. Beyond M&A and investment, Chinese EDA companies are accelerating their collaborations to achieve complementary advantages, a trend that is expected to continue to gain momentum in the future.

China’s EDA companies do encounter certain challenges during the integration process: (1) They lack prior experience in M&A and must continually learn and experiment. (2) Given the global semiconductor industry’s shifting dynamics, they may encounter obstacles from local governments when pursuing overseas M&A and investments.

As applications like AIGC, 8K, AR/MR, and others continue to develop, 3D IC stacking and heterogeneous integration of chiplet have become the primary solutions to meet future high-performance computing demands and extend Moore’s Law.

Major companies like TSMC and Intel have been expanding their investments in heterogeneous integration manufacturing and related research and development in recent years. Additionally, leading EDA company Cadence has taken the industry lead by introducing the “Integrity 3D-IC” platform, an integrated solution for design planning, realization, and system analysis simulation tools, marking a significant step towards 3D chip stacking.

Differences between 2.5D and 3D Packaging

The main difference between 2.5D and 3D packaging technologies lies in the stacking method. 2.5D packaging involves stacking chips one by one on an interposer or connecting them through silicon bridges, primarily used for assembling logic processing chips and high-bandwidth memory. On the other hand, 3D packaging is a technology that vertically stacks chips, mainly targeting high-performance logic chips and SoC manufacturing.

CPU and HBM Stacking Demands

With the rapid development of applications like AIGC, AR/VR, and 8K, it is expected that a significant amount of computational demand will arise, particularly driving the need for parallel computing systems capable of processing big data in a short time. To overcome the bandwidth limitations of DDR SDRAM and further enhance parallel computing performance, the industry has been increasingly adopting High-Bandwidth Memory (HBM). This trend has led to a shift from the traditional “CPU + memory (such as DDR4)” architecture to the “Chip + HBM stacking” 2.5D architecture. With continuous growth in computational demand, the future may see the integration of CPU, GPU, or SoC through 3D stacking.

3D Stacking with HBM Prevails, but CPU Stacking Lags Behind

HBM was introduced in 2013 as a 3D stacked architecture for high-performance SDRAM. Over time, the stacking of multiple layers of HBM has become widespread in packaging, while the stacking of CPUs/GPUs has not seen significant progress.

The main reasons for this disparity can be attributed to three factors: 1. Thermal conduction, 2. Thermal stress, and 3. IC design. First, 3D stacking has historically performed poorly in terms of thermal conduction, which is why it is primarily used in memory stacking, as memory operations generate much less heat than logic operations. As a result, the thermal conduction issues faced by current memory stacking products can be largely disregarded.

Second, thermal stress issues arise from the mismatch in coefficients of thermal expansion (CTE) between materials and the introduction of stress from thinning the chips and introducing metal layers. The complex stress distribution in stacked structures has a significant negative impact on product reliability.

Finally, IC design challenges from a lack of EDA tools, as traditional CAD tools are inadequate for handling 3D design rules. Developers must create their own tools to address process requirements, and the complex design of 3D packaging further increases the design, manufacturing, and testing costs.

How EDA Companies Offer Solutions

Cadence, during the LIVE Taiwan 2023 user annual conference, highlighted its years of effort in developing solutions. They have introduced tools like the Clarity 3D solver, Celsius thermal solver, and Sigrity Signal and Power Integrity, which can address thermal conduction and thermal stress simulation issues. When combined with Cadence’s comprehensive EDA tools, these offerings contribute to the growth of the “Integrity 3D-IC” platform, aiding in the development of 3D IC design.

“3D IC” represents a critical design trend in semiconductor development. However, it presents greater challenges and complexity than other projects. In addition to the challenges in Logic IC design, there is a need for analog and multi-physics simulations. Therefore, cross-platform design tools are indispensable. The tools provided by EDA leader Cadence are expected to strengthen the 3D IC design tool platform, reducing the technological barriers for stacking CPU, GPU, or SoC to enhance chip computing performance.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC)