According to TrendForce’s latest investigation, Chinese foundries have already suspended plans to expand production capacity for advanced processes after the US government began restricting the exportation of equipment and technical support for processes related to non-planar architectures. TrendForce believes that a further tightening of the restrictions on lithography equipment will mainly affect mature processes, especially the 28nm. Chinese foundries might proceed more slowly in adding new production capacity or raising output for the 28nm process due to the prolonged reviews on their equipment purchases.

TrendForce semiconductor analyst, Joanne Chiao, said that Chinese semiconductor companies have already suspended the development of chips featuring the GAA architecture (i.e., nodes that are generally ≤3nm) after the US government began restricting the exportation of EDA tools and related technical support. If we talk about the FinFET architecture that Chinese foundries are able to produce for now, it is possible to achieve the faster computing speed of the more advanced chips by combining multiple lower-end chips. However, it might also be very challenging to raise the production yield rate of a solution that integrates multiple chips, not to mention that the power consumption of such solution might be very high as well.

Seeing the US export control, for now, US government has not imposed restrictions on the exportation of technical support for processes related to planar architectures. On the other hand, Chinese foundries might halt their advanced chip (14nm) production at any time if they encounter an equipment malfunction or another problem that requires technical support from US equipment providers.

At last, Chiao emphasized that the US sanction has definitely accelerated the development of an “all-China” semiconductor manufacturing supply chain. Nevertheless, the world’s top eight semiconductor equipment providers all come from Japan or the US. From the perspective of the foundry industry, it will be hard for China to realize a wholly or mostly native semiconductor supply chain within the foreseeable future.

According to TrendForce, as the United States continues to expand the content of various lists, successively pass anti-China bills, and explicitly prohibit the export of certain products to China, the two countries have gradually drifted apart and this antagonistic relationship will continue if no drastic changes occur between the two parties in the next 6-8 years.

In the face of U.S. encroachment, all sectors in China must continue to look for escape routes if the country wishes to tear down the many walls built by the U.S. and move towards industrial autonomy. China’s top priority is to make breakthroughs in the semiconductor field. As far as current development is concerned, there are still many companies in China’s domestic IC design industry moving towards advanced manufacturing processes even after leading manufacturers such as Huawei, Changsha Jingjia Microelectronics, and Goke Microelectronics were placed on the entity list. At the same time, semiconductor manufacturers such as SMIC, CXMT, and Yangtze Memory Technologies have repeatedly developed advanced process technologies while Hua Hong Group has gradually expanded in the field of mature processes. If this trend continues, it will not be difficult for China to realize semiconductor autonomy in processes above 10nm.

If U.S. effectively enforces EDA ban and does not expand controls, impact on China will emerge in 2025

The U.S. Department of Commerce’s export restrictions on Chinese manufacturers are escalating but the autonomy of China’s domestic semiconductor industry is also gradually increasing. As the confrontation between the United States and China intensifies, the United States has launched a new wave of export control measures. On August 12, 2022, the U.S. Department of Commerce announced that it will restrict the export to China of EDA software required to design integrated circuits with GAAFET structure. Since GAAFET is a structure that is used in processes below 3nm, this move is equivalent to setting an advanced threshold for China’s semiconductor development.

Domestic Chinese IC designers who are committed to the development of SoCs, cloud computing chips, and GPUs are destined to move to more advanced manufacturing processes in order to meet the iterative needs of product upgrades and are expected to move toward the 4nm manufacturing process in the next 2 to 4 years. If the U.S. effectively implements the EDA software ban and does not expand the scope of EDA software restrictions, the impact of the ban on China’s semiconductor industry is expected to gradually emerge in 2025, not only delaying the development schedule of some domestic Chinese IC designers but even causing developmental stagnation.

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Although current semiconductor process technologies have evolved to the 3nm and 5nm nodes, SoC (system on a chip) architecture has yet to be manufactured at these nodes, as memory and RF front-end chiplets are yet to reach sufficient advancements in transistor gate length and data transmission performance. Fortunately, EDA companies are now attempting to leverage heterogeneous integration packaging technologies to link the upstream and downstream semiconductor supply chains as well as various IP cores. Thanks to this effort, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely continue to push the limits of Moore’s Law.

While SoC development has encountered bottlenecks, EDA tools are the key to heterogeneous integration packaging

As semiconductor process technologies continue to evolve, the gate length of transistors have also progressed from μm (micrometer) nodes to nm (nanometer) nodes. However, the more advanced process technologies are not suited for manufacturing all semiconductor components, meaning the development of SoC architectures has been limited as a result. For instance, due to physical limitations, memory products such as DRAM and SRAM are mostly manufactured at the 16nm node at the moment. In addition, RF front-end chiplets, such as modems, PA (power amplifiers), and LNA (low noise amplifiers) are also primarily manufactured at the 16nm node or other μm nodes in consideration of their required stability with respect to signal reception/transmission.

On the whole, the aforementioned memory, and other semiconductor components cannot be easily manufactured with the same process technologies as those used for high-end processors (which are manufactured at the 5nm and 3nm nodes, among others). Hence, as the current crop of SoCs is not yet manufactured with advanced processes, EDA companies including Cadence, Synopsys, and Siemens (formerly Mentor) have released their own heterogeneous integration packaging technologies, such as 2.5D/3D IC and SiP (system in package), in order to address the demand for high-end AI, SoC architecture, HPC (high performance computing), and optical communication applications.

EDA companies drive forward heterogeneous integration packaging as core packaging architecture and integrate upstream/downstream supply chain

Although the current crop of high-end semiconductor process technologies is still incapable of integrating such components as memory, RF front-end, and processors through an SoC architecture, as EDA companies continue to adopt heterogeneous integration packaging technology, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely extend the developmental limitations of Moore’s Law.

Information presented during Semicon Taiwan 2021 shows that EDA companies are basing their heterogeneous integration strategies mainly on the connection between upstream and downstream parts of the semiconductor supply chain, in addition to meeting their goals through chip packaging architectures. At the moment, significant breakthroughs in packaging technology design and architecture remain unfeasible through architectural improvements exclusively. Instead, companies must integrate their upstream chip design and power output with downstream substrate signal transmission and heat dissipation, as well as other factors such as system software and use case planning. Only by integrating the above factors and performing the necessary data analysis can EDA companies gradually evolve towards an optimal packaging architecture and in turn bridge the gap of SoC architectures.

With regards to automobiles (including ICE vehicles and EVs), their autonomous driving systems, electronic systems, and infotainment systems require numerous and diverse semiconductor key components that range from high-end computing chips to mid-range and entry-level MCUs. As such, automotive chip design companies must carefully evaluate their entire supply chain in designing automotive chip packages, from upstream manufacturers to downstream suppliers of substrates and system software, while also keeping a holistic perspective of various use cases. Only by taking these factors into account will chip design companies be able to respond the demands of the market with the appropriate package architectures．

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TrendForce’s investigations show that, among the three categories in the upstream semiconductor supply chain, which consist of semiconductor manufacturing equipment, materials, and EDA, China made the most progress regarding self-sufficiency in semiconductor equipment, followed by materials, with EDA coming in last, in 2020. In other words, Chinese companies are relatively slow to develop EDA solutions.

The EDA market is relatively oligopolistic and involves two US companies. That means once the US implements more stringent controls over the export of EDA technologies and products to China, China’s development of semiconductor self-sufficiency will most likely suffer dire consequences as a result. Even if Chinese domestic companies are able to supply semiconductor equipment for mature process nodes as well as technologies for chip design, manufacturing, and packaging/testing, these things are essentially inoperable without EDA software and technical support. That is to say, the EDA industry remains the final piece of the puzzle for China’s quest for semiconductor self-sufficiency. Since China’s new IC policies (termed the Policies for Promoting the High-Quality Development of the Integrated Circuit Industry and the Software Industry in the New Era) place more emphasis on semiconductor equipment, materials, and software, compared to past policies, EDA (for which China’s self-sufficiency rate is lower than 10%) will likely become the top developmental priority within the software category in the new IC policies.

Chinese EDA suppliers are likely to provide domestic substitute solutions for mature process nodes

As the Chinese semiconductor design and manufacturing industries continue to expand, the Chinese EDA software market is expected to grow at a 15.1% CAGR across 2020-2024, which is faster than the global average of 10.3%. Although Synopsys, Cadence, and Siemens still account for an approximately 80% share in the Chinese EDA market, domestic companies in China have been accelerating their pace of development in recent years. For instance, companies that have more than 10 years of experience developing EDA software, including S2C, Empyrean, Primarius, Xpeedic, NineCube, and Cellixsoft, are gradually making waves in the industry, while many other emerging companies, such as X-EPIC, Arcas, LEDA, and AMEDAC have also been attracting more attention in the EDA market recently. Now that China-US trade tensions have yet to be resolved, and China continues to proceed with its new IC policies, Chinese EDA suppliers will likely experience rapid growth going forward, especially in their attempt to create domestic substitutes for 28nm and other mature process technologies.

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