EDA


2023-10-10

[Report Highlights] China’s EDA Industry Enters a Period of Consolidation amidst Rapid Growth

China's EDA Industry into Fast Development with Efforts of Downstream Industries, Capital and Policies Propel Within the broader context of China's push for semiconductor self-sufficiency in recent years, the domestic EDA (Electronic Design Automation) industry in China has undergone remarkable g...

2023-09-08

Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era

As applications like AIGC, 8K, AR/MR, and others continue to develop, 3D IC stacking and heterogeneous integration of chiplet have become the primary solutions to meet future high-performance computing demands and extend Moore's Law. Major companies like TSMC and Intel have been expanding their i...

2023-02-09

[Chip War] The Latest Update of US Sanctions’ Impact on The Progress of Chinese Semiconductor Development

According to TrendForce’s latest investigation, Chinese foundries have already suspended plans to expand production capacity for advanced processes after the US government began restricting the exportation of equipment and technical support for processes related to non-planar architectures. TrendF...

2022-09-23

[Chip War] China’s Domestic Semiconductor Industry Looking to Break Embargo, Impact of EDA Ban to be seen in 2025

According to TrendForce, as the United States continues to expand the content of various lists, successively pass anti-China bills, and explicitly prohibit the export of certain products to China, the two countries have gradually drifted apart and this antagonistic relationship will continue if no d...

2022-01-14

Heterogeneous Integration Expected to Become Key Part of Packaging Technology Thanks to Development from EDA Companies

Although current semiconductor process technologies have evolved to the 3nm and 5nm nodes, SoC (system on a chip) architecture has yet to be manufactured at these nodes, as memory and RF front-end chiplets are yet to reach sufficient advancements in transistor gate length and data transmission perfo...

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