According to a report from the Commercial Times, Tokyo Electron (TEL), a leading global semiconductor equipment manufacturer, is the only company in the world that possesses equipment for four consecutive processes: deposition, coating/developing, etching, and cleaning, which are crucial steps before wafers enter the process of EUV lithography. As the semiconductor nodes keep advancing, the Japanese semiconductor giant would significantly benefit from the trend by its extensive product line.

Hiromitsu Kambara, TEL’s President & Representative Director of TEL Miyagi Ltd., stated that as chip design evolves, etching technology is continuously advancing towards 3D development, with vertical stacking making more efficient use of space. However, the increase in the number of stacking layers leads to an increase in the number of deposition cycles and etching times, thereby necessitating the growth in the number of required machines.

While EUV bellwether companies enjoy nearly 100% market share in the sector, TEL, with its close collaboration with the industry leader in the coating/developing process, could also dominate in this field, the report noted. In other words, as EUV shipments increase, TEL will benefit concurrently. TEL also disclosed that it has already established a research and development center in Taiwan and will soon expand its cleanroom facilities to collaborate with the most advanced process manufacturers.

When paired with partner Litho (lithography) machines, TEL has nearly 100% market share in the coating/developing market. Currently, TEL operates in 19 countries with a total of 87 locations, according to Commercial Times.

As the semiconductor industry enters the angstrom era, fabs are increasingly relying on equipment precision, for which TEL has prepared accordingly. TEL’s latest product, Grinder, is designed not only to ensure wafer flatness but also to achieve partial etching flatness and surface cleaning. This allows the equipment to measure wafers’ flatness and cleanliness effectively.

Previously, Huawei claimed its second-generation AI chip “Ascend 910B” could compete with NVIDIA’s A100 and was working to replace NVIDIA, which holds over 90% of the market share in China. However, Huawei is now facing significant obstacles in expanding its production capacity. According to a report from ChosunBiz, the chip is being manufactured by China’s leading semiconductor foundry, SMIC, and has been in mass production for over half a year, yet the yield rate remains around 20%. Frequent equipment failures have severely limited production capacity.

The report on June 27 states that despite being in mass production for over half a year, SMIC’s manufacturing of the Ascend 910B is still facing challenges, as four out of five chips still have defects. Meanwhile, due to increased U.S. export restrictions, the supply of equipment parts has been disrupted, causing production output to fall far short of targets.

SMIC initially projected an annual production of 500,000 units for the Ascend 910B, but due to continuous equipment failures, this goal has not been met. Currently, SMIC is unable to introduce new equipment and has to retrofit low-performance Deep Ultraviolet (DUV) equipment to replace advanced Extreme Ultraviolet (EUV) equipment for etching the 7nm circuits of the AI chips.

Dutch photolithography giant ASML stated that using EUV equipment for 7nm processes requires only nine steps, whereas using DUV equipment requires 34 steps. More steps lead to higher production costs, higher defect rates, and more frequent equipment failures. Additionally, the U.S. has further restricted global equipment manufacturers from providing maintenance services within China.

Industry sources cited by the same report reveal that SMIC lacks engineers for maintaining and managing chip manufacturing equipment, and global equipment suppliers are hesitant to provide services to China due to U.S. sanctions. SMIC is currently using equipment and parts purchased before the U.S. sanctions to maintain its 7nm production line.

According to a previous report by The Information, major tech companies such as Alibaba, Baidu, ByteDance, and Tencent have also been instructed to reduce their spending on foreign-made chips like NVIDIA’s. The Chinese government, which is aggressively promoting its own data center projects, is said to be boosting demand for Huawei’s AI chips as well.

Previously, the Wall Street Journal reported in January that Huawei received pre-orders for at least 5,000 Ascend 910B chips from Chinese tech giants last year, with delivery expected this year.

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Dutch semiconductor equipment giant ASML has hinted at the potential for receiving significant orders from key customer TSMC in the coming quarters, according to a June 5th report from Reuters.

Reuters, citing information disclosed at a Jefferies-hosted investor call, noted that ASML’s CFO, Roger Dassen, expressed optimism about the progress of commercial discussions with TSMC, suggesting they are close to concluding. Reportedly, it is anticipated that ASML could receive significant orders for 2-nanometer related equipment as early as the second or third quarter. The report also mentioned that TSMC is expected to receive ASML’s latest High-NA EUV lithography equipment sometime this year.

According to the report, ASML predicts strong demand continuing until 2026, driven primarily by government-subsidized fabs being built around the world.

As per Reuters, each High-NA EUV machine costs over EUR 350 million, and ASML has already received dozens of orders from customers, including Intel, TSMC, Samsung Electronics, SK Hynix, and Micron. Among these, Intel was the first to place an order and will be the first to receive the equipment.

Per a report from Bloomberg, TSMC had previously expressed concerns about the high pricing of ASML’s latest equipment. Kevin Zhang, Senior Vice President of Business Development at TSMC, stated during a technical symposium in Amsterdam on May 14th that the next-generation process “A16,” scheduled for release in the second half of 2026, may not necessarily require the use of High-NA EUV lithography equipment.

Dr. Kevin Zhang further remarked that while he appreciates the capabilities of High-NA EUV, he finds its price tag to be unlikeable.

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(Photo credit: ASML)

According to a report from a Japanese media outlet The Daily Industrial News, it reported that Micron Technology plans to build a new plant in Hiroshima Prefecture, Japan, for the production of DRAM chips, aiming to begin operations as early as the end of 2027.

The report estimates the total investment to be between JPY 600 billion and 800 billion (roughly USD 5.1 billion). Construction of the new plant is scheduled to begin in early 2026, with the installation of extreme ultraviolet (EUV) lithography equipment.

The Japanese government has approved subsidies of up to JPY 192 billion (roughly USD 1.3 billion) to support Micron’s production of next-generation chips at its Hiroshima plant. The Ministry of Economy, Trade and Industry stated last year that this funding would help Micron incorporate ASML’s EUV equipment, with these chips being crucial for powering generative AI, data centers, and autonomous driving technology.

Micron initially planned to have the new plant operational by 2024, but this schedule has evidently been adjusted due to unfavorable market conditions. Micron, which acquired Japanese DRAM giant Elpida in 2013, employs over 4,000 engineers and technicians in Japan.

Beyond 2025, Japan is set to witness the emergence of several new plants, including Micron Technology’s new 1-gamma (1γ) DRAM production facility in Hiroshima Prefecture.

JSMC, a foundry subsidiary of Powerchip Semiconductor Manufacturing Corporation (PSMC), is collaborating with Japan’s financial group SBI to complete construction by 2027 and begin chip production thereafter.

Additionally, Japanese semiconductor startup Rapidus plans to commence production of 2-nanometer chips in Hokkaido by 2027.

Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development.

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This May, we have witnessed two different approaches to the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment between semiconductor giants. Intel has secured the first batch of High-NA EUV kits from ASML, which will allegedly be used on its 18A (1.8nm) and 14A (1.4nm) nodes. On the other hand, TSMC stated that the company will not utilize this new lithography technology in its upcoming A16 (1.6nm) process.

High-NA EUV machines may be critical for companies aiming to produce chips beyond 2nm, but are they must-have?

Looking back in history, the industry used to believe that when the U.S. prevented EUV exports to China, the act would limit China’s progress in 7nm. However, China’s largest foundry, SMIC, is rumored to produce 5-nm chips for Huawei this year, without the need for EUV lithography machines.

When examining TSMC’s trajectory on EUV itself, it is worth mentioning that the company took a more cautious stance, as well. When Samsung began using EUV in its 7nm process in 2018, TSMC successfully launched its first 7nm production line using mature DUV lithography.

It was not until the stability and maturity of EUV had been confirmed that TSMC started to use EUV in its N7+ process, which took place in 2019. In the end, in spite of Samsung’s early adoption of EUV, yield issues allowed TSMC to overtake them.

Similarly, in the race for the 3nm process, unlike Samsung, instead of rushing to adopt GAAFET, TSMC chose the reliable FinFET route.

Will history repeat itself? Now it would be a good timing to examine TSMC’s strategy on High-NA EUV machines.

High-NA EUV technology: A Cure for All?

According to a report by China’s Jiwei, at the recent 2024 North America Technology Symposium hosted by TSMC, the company revealed that its A16 process would not require the next-generation High-NA EUV lithography machines, with mass production expected in 2026.

An expert cited by Jiwei stated that TSMC’s decision might be due to the higher risk associated with High-NA lithography machines.

The report noted that there would be still quite a few challenges to be resolved, such as supporting light sources for photon shot noise and productivity requirements, solutions for the 0.55 NA’s small depth of focus, computational lithography capabilities, mask manufacturing, and computing infrastructure including new materials. Not to mention there is the necessary debugging and development time to ensure stability, which implies considerable time and hidden costs.

On the other hand, TSMC began to adopt EUV in its N7+ process in 2019, implying the world’s largest chipmaker has committed plenty of time and effort to refine the technology.

According to the report by Jiwei, by optimizing the EUV exposure dose and the photoresist used, as well as improving photomask life, increasing yield, and reducing defect rates, TSMC has achieved significant advancements. Today, the number of EUV lithography machines has increased tenfold, while wafer output nowadays is 30 times that of 2019.

Weigh Between Cost and Technology

In addition to potential technology bottlenecks, higher cost may be another problem. Per a report from Bloomberg, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that while he appreciates the capabilities of High-NA EUV, he finds its price tag to be unlikeable.

As per the same report from Bloomberg, ASML’s new High-NA EUV machine is priced at EUR 350 million (roughly USD 380 million). Jiwei further stated the unit price may more than double, comparing with the current EUV machines (roughly EUR 170 million).

Market demand would be another major concern. Citing an industry insider, Jiwei analyzed that the cost of manufacturing chips with High-NA lithography machines increases significantly. While more chips can be cut from each wafer, more chips need to be sold to recoup the investment.

The report stated that the smartphone AP chip market alone cannot absorb these cost without the supporting demand of AI chips. However, as China, the largest market for AI, is now being restricted by export control measures from the U.S., the overall market demand remain uncertain.

Adoption Timing for High-NA EUV? TSMC May Not Be in a Hurry

Then what would be the right timing for TSMC to adopt High-NA EUV?

The report by Jimwei took the trajectory of EUV as an example. When the industry generally regarded EUV essential in the 7nm node, TSMC successfully launched its first 7nm production line using mature DUV lithography. This strategy allowed TSMC to avoid the imperfections and high costs of EUV lithography at that time.

TSMC waited until 2019 to start the usage of EUV in its N7+ process when the technology has become mature enough. In the end, in spite of Samsung’s early adoption of EUV, yield issues allowed TSMC to win the favor of clients.

Similarly, in the race for the 3nm process, instead of rushing to adopt GAAFET, TSMC chose the reliable FinFET route. Despite Samsung’s early lead with 3nm, their low yields and repeated delays enabled TSMC to surpass them.

TSMC’s previously announced roadmap indicates that the 1.4nm A14 process is expected to be introduced between 2027 and 2028, while the development of the 1nm A10 process is projected to be completed before 2030. The report by Jiwei suggested that TSMC might consider using the next-generation lithography machine only after the 1nm process is in place, potentially adopting the High-NA EUV system around 2029 to 2030.

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(Photo credit: ASML)