TSMC, along with research teams like imec, continues to push the boundaries in pursuit of optimal solutions for achieving high bandwidth and low power consumption on the same chip area.

As per a report from Commercial Times, Imec has even mapped out a blueprint for the Angstrom era, with the potential to surpass the A1 threshold by 2040. They have also revealed that the A14 node will require the adoption of High-NA EUV (Extreme Ultraviolet Lithography with High Numerical Aperture), reportedly hinting that TSMC’s adoption of High-NA EUV is inevitable.

Per another report from the Economic Daily News, Luc Van den hove, President and CEO of imec, presented imec’s latest technological roadmap at the ITF Taiwan 2024 forum. He outlined plans to advance to the 2nm node by 2025, enter the angstrom era with the A14 process by 2027, and reach the A2 process by 2037.

He also explained the changes in imec’s transistor architecture, stating that the 2nm process will transition from FinFET to Nanosheet architecture, while the A7 process will further shift to complementary FET (CFET) architecture.

This, per Commercial Times’ report, hints that TSMC’s adoption is only a matter of time. TSMC emphasized that whenever new structures and tools, such as High-NA EUV, emerge, they carefully evaluate their maturity, costs, schedules, and feasibility.

Min Cao, Vice President of R&D at TSMC, pointed out that the performance, power, and area (PPA) gains from field-effect transistors (FETs) are diminishing. To sustain high growth, TSMC does not rule out the development of emerging materials.

He further expressed optimism about the significant growth wave driven by artificial intelligence, noting that the complexity of AI models and computational power is expected to grow exponentially.

Min Cao noted that the automotive sector will soon adopt 3nm and 5nm chips, and TSMC will be able to support the advancement of autonomous driving. He estimated that the semiconductor market will reach a scale of USD 1 trillion by 2030.

Read more

• [News] TSMC’s Expansion beyond 2nm Taking Shape? Angstrom-Class Fabs Possibly in Southern Taiwan
• [News] Decipher TSMC’s Calm Take on High-NA EUV Lithography Machines: Who May Have the Last Laugh in the Angstrom Era?

(Photo credit: TSMC)

TSMC is set to offer a new round of its CyberShuttle prototyping service in September. According to sources cited in a report from Commercial Times, it’s revealed that, as per usual practice, there are two opportunities each year, in March and September, for customers to submit their projects. It is indicated that the highlight this time is expected to be the 2nm process, providing leading companies with an opportunity to gain an edge.

TSMC’s 2nm technology is progressing smoothly, with the new Hsinchu Baoshan plant on track for mass production next year. Previously, there were rumors indicating that Apple is considering adopting 2nm chips in 2025, with the iPhone 17 series potentially being among the first devices to use them.

Reportedly, both TSMC’s N2P and A16 technologies are expected to enter mass production in the second half of 2026, offering improvements in power efficiency and chip density.

ASIC companies are eagerly participating in CyberShuttle this time, even though customer intentions for the first 2nm tape-out are still unconfirmed. However, this technology will likely maintain TSMC’s leadership in advanced processes, securing its future technological advantage.

CyberShuttle, also known as MPW (Multi-Project Wafer), refers to the process of placing chips from different customers onto the same test wafer. This approach not only allows for the shared cost of photomasks but also enables rapid chip prototyping and verification, enhancing customers’ cost efficiency and operational effectiveness.

Based on TSMC’s official information, the CyberShuttle prototyping service significantly reduces NRE costs by covering the widest technology range (from 0.5um to 7nm) and the most frequent launch schedule (up to 10 shuttles per month), all through the Foundry segment’s most convenient on-line registration system.)

TSMC’s CyberShuttle prototyping service also validate the sub-circuit functionality and process compatibility of IP, standard cell libraries and I/Os, reducing prototype costs by up to 90%. TSMC states that their current CyberShuttle service covers the broadest range of technologies and can offer up to 10 shuttles per month.

TSMC’s 2nm technology is expected to make its debut in September, offering opportunities for test chips.

Per the report from Commercial Times, IC design companies have pointed out that, unlike the familiar FinFET (Fin Field-Effect Transistor) structure, the industry is transitioning to the Gate-All-Around FET (GAAFET) structure, making it crucial for the market to quickly adapt.

This also allows IC design companies to provide related products to end customers, demonstrating their 2nm design capabilities.

ASIC companies have also revealed that, based on CyberShuttle data, the number of advanced process projects below 7nm is relatively small, with mature processes still dominating.

This suggests that future competition will likely focus on a few leading companies. Those who miss the first wave of 2nm technology may fall behind their competitors by up to six months, making securing a spot on the Shuttle even more critical.

Read more

• [News] TSMC Reportedly to Raise 3nm & 5nm Prices Soon, Looking to Maintain Long-Term Profit Margins 
• [News] Apple Not Adopting TSMC 2nm for iPhone 17? A19 Pro Chip Rumored to Use N3P Process

(Photo credit: TSMC)

With the United States expected to further restrict China from acquiring advanced GAA (Gate-All-Around) chip architecture capabilities, coupled with reports of poor yield rates in Samsung’s 3nm GAA generation, the semiconductor industry sources cited in a report from Commercial Times state that TSMC’s 3nm FinFET process is enjoying dominance. Reportedly, due to the high demand and limited supply capacity, upstream IC design companies are beginning to report price hikes.

Seven global tech giants, including NVIDIA, AMD, Intel, Qualcomm, MediaTek, Apple, and Google, are set to gradually adopt TSMC’s 3nm process. As per the sources cited in the report from Commercial Times, Qualcomm’s Snapdragon 8 Gen 4, built using TSMC’s N3E process, has seen a price increase of 25% compared to the previous generation, potentially triggering a subsequent trend of price hikes.

Samsung was the first to commence mass production of 3nm chips using the GAA process in June 2022. However, the first-generation N3 node, SF3E, did not achieve significant success and was initially limited to cryptocurrency applications. Subsequently, the yield rate for its own Exynos 2500 chip also fell short of expectations.

Additionally, Google’s Tensor processors, which are manufactured by Samsung, still use Samsung’s 4nm process in their fourth generation. However, it is said in the report that the fifth generation will switch to TSMC’s 3nm process.

In the second half of the year, numerous AI products will be launched in the consumer market. Among the three major players in the mobile chip market, Qualcomm’s Snapdragon 8 Gen 4, MediaTek’s Dimensity 9400, and Apple’s A18 and M4 series will all be built using TSMC’s N3 family. Moreover, Google’s Tensor G5 will also compete in the market.

It is rumored that Qualcomm’s Snapdragon 8 Gen 4 has already initiated the first wave of price increases. The industry sources cited in the report claim that the procurement cost of mobile chips was already high, with last year’s flagship 8 Gen 3 costing around USD 200. This year’s flagship chip might exceed USD 250. Whether competitors will follow suit remains to be seen.

However, industry sources cited by the report also point out that the price increase is within a reasonable range. Compared to the 5nm process, the cost per wafer for the 3nm process is about 25% higher. This increase does not yet take into account overall wafer quantities and design architecture factors.

TSMC President C.C. Wei has also revealed that TSMC products are highly power-efficient and have better yield rates. When considering the cost per chip, TSMC is the most cost-effective.

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] NVIDIA CEO Jensen Huang Supports C.C. Wei’s Theory and Backs for TSMC to Increase Price

(Photo credit: TSMC)

The U.S. Department of Commerce announced new semiconductor restrictions on October 7 in the United States. In addition to existing restrictions on the logic IC sector, this new update extends to the memory category. In addition to Chinese-funded enterprises, the extent of these restrictions stipulate foreign-owned production centers located in China will also need to apply for approval on a case-by-case basis in order to continue to obtain manufacturing-related equipment. In addition, the new restrictions increase the difficulty for China to obtain any chips that may be used for military purposes through imports.

According to TrendForce research, the scope of this update is primarily limited to 16nm, 14nm, or more advanced proceses for logic ICs (such as FinFET or GAAFET), 18nm or more advanced processes for DRAM, and 128-layer or higher products for NAND Flash chips.

Analysis of impact on foundry industry

In terms of foundry equipment supply, after SMIC was included on the Entity List in 2020, according to TrendForce investigations, the US Department of Commerce targeted US equipment manufacturers who wished to export equipment used for processes below 16nm (inclusive) to Chinese fabs not included on the Entity List including HuaHong Group, etc., and even foreign-owned production centers located in China, instituting a review before export can be implemented. Therefore, most Chinese fabs are currently focusing their production expansions on processes 28nm and above. As for non-Chinese wafer foundries, only TSMC Nanjing is focused on 28nm expansion and has no plan for advanced processes.

TrendForce indicates, although Chinese fabs are actively partnering with domestic Chinese, European, and Japanese equipment manufacturers in an attempt to develop non-US centric production lines and have turned to the development of 28nm and above processes, the ban is completely stifling the possibility for China to develop and expand advanced processes 16nm and below and the expansion of processes 28nm and above is also subject to a protracted review process.

In addition, the US ban will expand the scope of its restrictions following the inclusion of high-end GPUs such as NVIDIA’s A100/H100 and AMD’s MI250 in the HPC sector into the range of sanctions at the end of August. In the future, it will target US manufacturers, including HPC sector CPUs, GPUs, and AI accelerators used in datacenter, AI, and supercomputer applications, requiring review before such items can be exported to China. In addition, foundries may no longer be able to manufacture any of the above-mentioned HPC-related chips for any Chinese IC design houses. TrendForce believes, regardless of whether the client is a Chinese or American IC design house, most HPC-related chips are currently manufactured by TSMC with mainstream processes at the 7nm, 5nm, or certain 12nm nodes. In the future, whether the situation is American factories no longer being able to export to the Chinese market or Chinese factories being unable to initiate projects and mass produce wafer starts, it will all have a negative impact on the future purchase order status of TSMC’s 7nm and 5nm processes.

Analysis of impact on memory industry

TrendForce indicates, according to the new specifications announced by the U.S. Department of Commerce, the DRAM portion of sanctions will be limited to the 18nm process (inclusive) and equipment must be reviewed by the Department before import. This move will greatly restrict or delay the sustainable development of China’s DRAM sector. CXMT possesses the largest memory market share for a Chinese company in the domestic Chinese market. Since 2Q22, the company has been committed to moving from the 19nm process into the 17nm process. Although the purchase of machinery to fulfill future needs had been accelerated before the ban, volume is still insufficient. CXMT continues to build new plants, including Phase 2 in Hefei and SMBC (SMIC Jingcheng), which is in discussion with SMIC. All of these projects will face difficulties in obtaining equipment in the future.

In addition to CXMT, the C2 plant of SK hynix’s DRAM production center in Wuxi is also affected by the restriction order. The factory accounts for approximately 13% of the world’s total DRAM production capacity and its process has evolved to 1Ynm and more advanced nodes, which means that subsequent continuous addition of equipment required for production requires approval on a case-by-case basis.

TrendForce has also observed, considering geopolitics, although current market demand is sluggish and supply and demand are seriously imbalanced, the three major manufacturers in the DRAM market still plan to increase production capacity in their home countries in the next 10 years and continue to reduce the proportion of production in China.

In terms of NAND Flash, TrendForce indicates that the import of NAND production equipment into China will be further restricted in the future, especially for equipment used in the manufacture of product of 128 layers and above (inclusive), requiring prior approval before import. It is estimated that this ban will significantly impact the long-term plans of China’s YMTC to upgrade its factory campuses as well as Samsung’s Xi’an plant and Solidigm’s process migration plan in Dalian.

TrendForce indicates that this ban will restrict YMTC from further expanding its customer base. At this stage, YMTC has been aggressively sending SSD products out for verification, hoping to successfully infiltrate the supply chain of non-Chinese customers in 2023. In the future, as the impact of the ban materializes, the US government will impose stricter restrictions on the development of China’s memory industry which will greatly limit non-Chinese customers’ adoption and consideration of YMTC.

（Image credit: iStock）