As the COVID-19 pandemic wreaked havoc on the global electronics supply chain, the packaging and testing operations of mid-range and high-end chips were subsequently confronted with prolonged lead times. This can primarily be attributed to the fact that IC substrate suppliers were unable to raise output or expand their production capacities in the short run in order to meet the skyrocketing volume of client orders. Hence, products that are packaged using BGA (Ball Grid Array), Flip Chip, or SiP technologies, all of which require the use of IC substrates, had their lead times lengthened. Certain IC design companies are therefore considering the feasibility of packaging technologies that do not require substrates.

Regarding the trend of advanced packaging development, technologies such as 2.5D/3D IC, SiP, and FOPLP (Fan-out Panel Level Packaging) remain the current mainstream R&D targets. Given the ongoing shortage of semiconductor components, including IC substrates, FOPLP, in particular, has garnered the most attention among the aforementioned three packaging technologies as it can be operated without substrates. At present, most OSAT companies and other chipmakers have successively invested in FOPLP-related technological and manufacturing development in order to capitalize on potential new commercial opportunities.

Despite FOPLP’s advantage of packaging chips across large areas, technological development remains problematic

Regarding the history of FOPLP development as well as the technology’s evolution going forward, its earliest roots can be traced to existing packaging applications including Flip Chip and BGA. As end-products continued to experience performance upgrades, leading to the number of I/O pins being insufficient for meeting the increase in performance demand, new types of wafer-level packaging technologies such as Fan-in and Fan-out subsequently emerged to fulfill the packaging demands of mid-range chips, high-end chips, and other emergent applications.

Although Fan-in and Fan-out packaging technologies are able to effectively raise the number of I/O pins, they also result in a substantial increase in manufacturing costs compared to previous-generation technologies such as Flip Chip and BGA. For both 8-inch wafers and 12-inch wafers, packaging costs have only been on a very slight downtrend. That is why the packaging industry has placed a top priority on simultaneously lowering production costs while raising the number of chips packaged at once. Hence, FOPLP technology has emerged in response to this demand for large-area packaging technology.

Regarding the actual implementation of FOPLP, a potential solution may be found in wafer-level packaging RDL (Redistribution Layer) designs, such as chip first or chip last. It should be noted that chip first FOWLP or chip last FOWLP processes do in fact serve as feasible concepts for FOPLP development. However, the FOPLP process involves stacking massive amounts of packaging materials and chips together, and their combined weight may lead to such issues as panel warpage. In addition, it remains difficult to maintain a consistent uniformity and yield rate during the FOPLP process, meaning further collaborations and optimizations on the parts of OSAT companies and semiconductor equipment suppliers are necessary for FOPLP to succeed going forward.

（Image credit: Unsplash）