According to a report from Economic Daily News, Foxconn Group is advancing into the field of advanced packaging with a strategic alliance between Taiwan and Japan, focusing on the trending panel-level fan-out packaging (FOPLP). Following Innolux’s related developments in Taiwan, another of Foxconn’s invested companies, Sharp, has announced its entry into panel-level fan-out packaging in Japan, with production capacity expected in 2026.

Foxconn Group already possesses a comprehensive capability in the AI sector, and with the key advanced packaging technology now in place, they are fully mobilized. On the other hand, Sharp is undergoing a major transformation, which also benefits Foxconn— as its subsidiary Foxconn Technology is a major shareholder in Sharp, and Pan International is a partner with Sharp, both of which stand to gain from this transformation and provide support for it.

Pan International has previously collaborated with Sharp in areas such as wire harnesses, PCBs, and optical components, and has also acted as a distributor for Sharp’s panels and optoelectronic components. With Foxconn Chairman Young Liu concurrently serving as Sharp’s chairman, along with Sharp scaling down its panel business and expanding its semiconductor operations, there is significant interest in whether there will be new collaborations between the two companies.

Earlier, Sharp announced that it is partnering with Japanese electronic component manufacturer Aoi Electronics to advance into the field of advanced packaging. Reportedly, an agreement has been signed between Aoi, Sharp, and Sharp Display Technology, under which Aoi will utilize Sharp’s panel facilities to build a semiconductor back-end process production line. In 2024, Aoi will establish an advanced semiconductor panel packaging production line at Sharp’s Mie Plant, aiming for full-scale production by 2026 with a monthly capacity of 20,000 wafers.

Nikkei previously reported that Sharp continues to downsize its panel plants while expanding semiconductor production. Sharp noted that the advanced packaging production line will be used to produce Aoi’s FOLP. According to the agreement, the three companies are considering cooperation in the semiconductor back-end process to expedite the establishment of production lines and achieve full-scale production.

Read more

• [News] Foxconn’s Young Liu Newly Elected as Sharp’s Chairman to Assist Transformation
• Sharp Announces Closure of Sakai Gen 10 Line, Supply Cut of 5 Million TV Panels Expected in 2025, Says TrendForce

(Photo credit: Foxconn)

TSMC is said to be entering the fan-out panel-level packaging (FO-PLP) sector, according to a previous report from Nikkei. Now, a report from Business Korea noted that Samsung is making significant strides in the PLP field, as the tech giant acquired the PLP business from Samsung Electro-Mechanics as early as in 2019.

It is interesting to note that TSMC has returned to the development of PLP now, while this technology is actually regarded by Samsung as the “secret weapon” to challenge TSMC’s InFO-WLP technology a few years ago.

In 2015, TSMC has secured all of Apple’s A10 orders by offering the InFO-WLP (Integrated Fan-Out Wafer Level Packaging) technology. According to a previous report by Korea media outlet ETNews, Samsung was prompted to take action, making the company to cooperate with Samsung Electro-Mechanics to start developing FO-PLP technology.

In 2019, Samsung acquired the PLP business from Samsung Electro-Mechanics for 785 billion won (approximately USD 581 million), a strategic move that has paved the way for its current advancements, according to Business Korea.

At the shareholders’ meeting in March this year, Kyung Kye-hyun, the former head of Samsung Electronics’ semiconductor (DS) division, highlighted the importance of PLP technology to the industry, Business Korea noted. Kyung stated that AI semiconductor dies, which are typically 600mm x 600mm or 800mm x 800mm in size, require technologies like PLP, while Samsung is actively developing this technology and collaborating with clients.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

On the other hand, TSMC is reportedly collaborating with equipment and material suppliers to develop the panel-level packaging technology, though the research is still in its early stages. By using a rectangular substrate for packaging, replacing the current traditional circular wafer, more chipsets can be accommodated on a single wafer.

The report by Nikkei mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

For now, TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips soon. The reason behind TSMC’s foray into PLP research, therefore, may be interpreted as a response to the booming AI demand.

Read more

• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] New Battleground for TSMC, Samsung & Intel in Panel-Level Packaging

(Photo credit: Samsung)

As the COVID-19 pandemic wreaked havoc on the global electronics supply chain, the packaging and testing operations of mid-range and high-end chips were subsequently confronted with prolonged lead times. This can primarily be attributed to the fact that IC substrate suppliers were unable to raise output or expand their production capacities in the short run in order to meet the skyrocketing volume of client orders. Hence, products that are packaged using BGA (Ball Grid Array), Flip Chip, or SiP technologies, all of which require the use of IC substrates, had their lead times lengthened. Certain IC design companies are therefore considering the feasibility of packaging technologies that do not require substrates.

Regarding the trend of advanced packaging development, technologies such as 2.5D/3D IC, SiP, and FOPLP (Fan-out Panel Level Packaging) remain the current mainstream R&D targets. Given the ongoing shortage of semiconductor components, including IC substrates, FOPLP, in particular, has garnered the most attention among the aforementioned three packaging technologies as it can be operated without substrates. At present, most OSAT companies and other chipmakers have successively invested in FOPLP-related technological and manufacturing development in order to capitalize on potential new commercial opportunities.

Despite FOPLP’s advantage of packaging chips across large areas, technological development remains problematic

Regarding the history of FOPLP development as well as the technology’s evolution going forward, its earliest roots can be traced to existing packaging applications including Flip Chip and BGA. As end-products continued to experience performance upgrades, leading to the number of I/O pins being insufficient for meeting the increase in performance demand, new types of wafer-level packaging technologies such as Fan-in and Fan-out subsequently emerged to fulfill the packaging demands of mid-range chips, high-end chips, and other emergent applications.

Although Fan-in and Fan-out packaging technologies are able to effectively raise the number of I/O pins, they also result in a substantial increase in manufacturing costs compared to previous-generation technologies such as Flip Chip and BGA. For both 8-inch wafers and 12-inch wafers, packaging costs have only been on a very slight downtrend. That is why the packaging industry has placed a top priority on simultaneously lowering production costs while raising the number of chips packaged at once. Hence, FOPLP technology has emerged in response to this demand for large-area packaging technology.

Regarding the actual implementation of FOPLP, a potential solution may be found in wafer-level packaging RDL (Redistribution Layer) designs, such as chip first or chip last. It should be noted that chip first FOWLP or chip last FOWLP processes do in fact serve as feasible concepts for FOPLP development. However, the FOPLP process involves stacking massive amounts of packaging materials and chips together, and their combined weight may lead to such issues as panel warpage. In addition, it remains difficult to maintain a consistent uniformity and yield rate during the FOPLP process, meaning further collaborations and optimizations on the parts of OSAT companies and semiconductor equipment suppliers are necessary for FOPLP to succeed going forward.

（Image credit: Unsplash）