According to the news from ChinaTimes, the semiconductor market is experiencing a slowdown, with Taiwan’s three major mature process wafer foundries UMC, VIS, and PSMC all reporting reduced revenues in August. VIS and UMC both posted lower revenues compared to the previous month, while PSMC managed a slight 1.2% monthly increase in August. However, this increase still falls within this year’s relatively low range. Industry experts anticipate that the semiconductor industry will maintain a subdued market outlook in the latter half of this year, with a potential recovery likely delayed until the first half of the next year.

The semiconductor industry began its correction in the second half of last year. Initially, there was optimism for inventory adjustments to conclude within four quarters by the end of this year’s second quarter, anticipating a demand rebound in the latter half of the year. However, since the second quarter, semiconductor manufacturers have grown pessimistic due to slower downstream inventory depletion and weak end-user demand. This is reflected in third-quarter revenues for mature process wafer foundries, which are expected to remain flat or slightly decline based on August revenues. A robust recovery in the fourth quarter is unlikely, suggesting that industry-wide recovery is likely postponed until the first half of next year.

UMC saw consecutive monthly revenue growth from February to July. However, following five consecutive increases, the company experienced a slight decrease in revenue in August. TSMC previously stated in a conference that the current market recovery falls short of expectations, with an unclear outlook for wafer demand. It anticipates a 3~4% quarter-on-quarter decrease in wafer shipments in the third quarter, which aligns with the market’s expectations for a slight decline in August revenue.

UMC forecasts a 3~4% quarter-on-quarter decrease in wafer shipments in the third quarter, a 2% quarter-on-quarter increase in the average wafer price in USD, a low single-digit percentage decrease in the average gross margin, and an approximate 65% capacity utilization rate. Overall, industry insiders expect TSMC to face slight downward pressure on third-quarter revenue.

VIS reported July revenue reaching NT$3.596 billion, marking a new high for the first seven months of the year. However, its August revenue showed a decline, with a 2.23% month-on-month decrease to NT$3.516 billion. This is significantly different from the typical revenue growth momentum observed during the third-quarter peak season in previous years. Cumulative revenue for the first eight months of this year also decreased by 34.54% compared to the same period last year.

VIS anticipates a 4~6% quarter-on-quarter increase in wafer shipments in the third quarter, with a capacity utilization rate similar to that of the second quarter, around 60%. The average selling price (ASP) is expected to remain stable. However, due to increased production costs and depreciation expenses, the gross margin is estimated to decline to 25~27% in the third quarter, putting more pressure on profitability compared to revenue.

As for PSMC, although its August revenue saw a slight 1.2% month-on-month increase, the company has maintained around NTD 3.4 billion in monthly revenue from June to August, which is considered a low level compared to the second quarter when monthly revenue was approximately NTD 3.8 billion. The third quarter is expected to continue to exert downward pressure on revenue compared to the previous quarter. The company has also previously stated that it does not rule out the possibility of a quarterly loss in its core business during the third quarter.

(Source: https://www.chinatimes.com/newspapers/20230911000124-260202?chdtv)

In recent market speculations, TSMC is rumored to have reduced its 8-inch wafer manufacturing quotes by as much as 30%, with subsequent reports suggesting that South Korean wafer foundries are following suit in lowering 8-inch wafer production prices.

According to TrendForce’s channel check, TSMC’s current strategy for 8-inch processes involves bundling spot deal negotiations with one-time pricing or offering discounts and rebates on initial NRE fees, without implementing an across-the-board price cut.

However, observations from the order books indicate a genuine decline in demand for 8-inch products. Presently, customers have started revising their orders through the first quarter of 2024. The possibility of TSMC reducing prices for 8-inch wafers cannot be ruled out.

Similarly, the industry has also seen reports of South Korean wafer foundries Samsung and Dongbu HiTek considering price reductions for their 8-inch wafer plants. TrendForce indicates that the price adjustments in South Korea’s 8-inch wafer foundries follow a similar pattern of spot deal reductions, primarily centered around one-time negotiations. Customers with long-term agreement already have lower prices, without any instances of price reduction.

Both 12-inch and 8-inch wafer fabrication utilization rates have shown less-than-expected recovery, leading TrendForce to estimate a year-on-year decrease of around 13% in the overall semiconductor foundry revenue for 2023.

(Photo credit: TSMC)

As per a report from Taiwan’s TechNews,” TSMC, Samsung, and Intel have been actively deploying Backside Power Delivery Network (BSPDN) strategies recently, and have announced plans to incorporate BSPDN into their logic chip development roadmap. For instance, Samsung intends to implement BSPDN technology in its 2-nanometer chips, a move unveiled at the VLSI Symposium in Japan.

According to imec, BSPDN aims to alleviate the congestion issues faced by front-end logic chips in later-stage processes. Through Design Technology Co-Optimization (DTCO), more efficient wire designs are achieved in standard cells, aiding in the downsizing of logic standard cell.

In essence, BSPDN can be seen as a refinement of chiplet design. The conventional approach, where logic circuits and memory modules are integrated, is transformed into a configuration with logic functions on the front and power or signal delivery from the back.

While the traditional method of front-side wafer power delivery achieves its purpose, it leads to decreased power density and compromised performance. Nevertheless, the new BSPDN technique has not yet been adopted by foundries.

Samsung claims that, compared to the conventional method, BSPDN reduces area by 14.8%, providing more chip space for additional transistors and improved overall performance. Wire lengths are also cut by 9.2%, reducing resistance, allowing greater current flow, and thereby lowering power consumption while enhancing power transmission efficiency.

In June of this year, Intel also introduced its BSPDN-related innovations under the name ‘PowerVia.’ Team Blue plans to utilize this approach in the Intel 20A process, potentially achieving a chip utilization rate of 90%.

Intel believes PowerVia will address interconnect bottlenecks in silicon architecture, enabling continuous transmission through backside wafer powering. The company anticipates incorporating this novel approach into its Arrow Lake CPUs slated for release in 2024.

Furthermore, according to Taiwan’s supply chain sources, TSMC remains on track to launch its 2-nanometer process in 2025, with mass production expected in the latter half of the year in Hsinchu’s Baoshan. The company’s N2P process, planned for 2026, will feature BSPDN technology.

(Photo credit: Samsung)

According to the news from Mydrivers.com, TSMC announced its ambitious plans for constructing cutting-edge 4nm and 3nm chip fabs in the United States. The move is expected to generate tens of thousands of job opportunities in the US job market. However, TSMC’s timeline for commencing production at its inaugural 4nm fab has been pushed back from 2024 to 2025. The attributed cause behind this delay is the insufficient availability of skilled American workers, causing setbacks in equipment installation.

This situation has led to a heated dispute between TSMC and local labor unions. TSMC’s assertion of a skilled worker deficit in the US has sparked disagreement from the unions. They assert that TSMC’s stance is a pretext for bringing in lower-wage overseas labor to vie for domestic employment opportunities. TSMC, on the other hand, refutes these claims, emphasizing that employing local staff on assignment doesn’t undermine their US-based operations or recruitment efforts.

Apart from the skill-related quandary, the delay in TSMC’s factory plans may have an underlying factor – the scorching conditions in Phoenix, Arizona. Sources report that the city has experienced an unbroken streak of over 20 days with temperatures hovering around 43 degrees Celsius. Notably, this heat wave has raised internal questioning within TSMC about the wisdom of selecting a desert-adjacent location for their facility.

According to this industry insider, the intense heat seemingly played a role in impeding progress. The sweltering climate of over 40 degrees Celsius undoubtedly hampers worker productivity, particularly for outdoor tasks.

The informer indicated that TSMC had an alternative option when choosing a location for its US facility. Aside from Arizona, they could have set up shop in Portland, the capital of Oregon, which is also a hub for the semiconductor industry. However, TSMC’s rationale for settling in Arizona remains undisclosed.

Notably, Phoenix, Arizona, is also a focal point for Intel’s chip investments, with the company injecting 20 billion USD into the establishment of new wafer fabs over the past couple of years.

(Source: https://news.mydrivers.com/1/928/928753.htm)

According to a report by Taiwan Economic Daily, industry sources have revealed that due to sluggish terminal demand and market competition, TSMC and Vanguard have recently been progressively lowering their prices for 8-inch wafer foundry services, with reductions as high as 30%.

While 8-inch wafer foundry services do not constitute a major portion of TSMC’s revenue, the company has historically maintained a relatively steadfast pricing strategy, refraining from frequent price hikes or reductions. The current reduction of up to 30% has raised significant attention.

The report states that the semiconductor industry is experiencing a downturn in prosperity, resulting in decreased capacity utilization at wafer foundries. Within this context, demand for 8-inch wafers is weaker compared to 12-inch wafers, leading some manufacturers to see their 8-inch wafer utilization rates drop to around 60%.

Regarding the price reduction, analysts at Nomura Securities suggest that this move is primarily aimed at countering Texas Instruments (TI), a global leader in analog ICs, which has significantly lowered prices for products such as power management ICs, triggering a worldwide semiconductor price war that has impacted related industries. In response, IC design companies are hoping for price reductions from foundries such as TSMC and to lower costs and compete against TI.

IC design firms have indicated that they have not received any official notification of price reductions for 8-inch wafer foundry services. They emphasized that TSMC has never implemented such a substantial reduction of up to 30% since its establishment, raising doubts about the authenticity of the news. TSMC has declined to comment on pricing matters.

(Photo credit: TSMC)