According to the South Korean media The Korea Economic Daily’s report, Samsung Electronics has established a new business unit dedicated to developing next-generation chip processing technology. The aim is to secure a leading position in the field of AI chips and foundry services.

The report indicates that the recently formed research team at Samsung will be led by Hyun Sang-jin, who was promoted to the position of general manager on November 29. He has been assigned the responsibility of ensuring a competitive advantage against competitors like TSMC in the technology landscape.

The team will be placed under Samsung’s chip research center within its Device Solutions (DS) division, which oversees its semiconductor business, as mentioned in the report.

Reportedly, insiders claim that Samsung aims for the latest technology developed by the team to lead the industry for the next decade or two, similar to the gate-all-around (GAA) transistor technology introduced by Samsung last year.

Samsung has previously stated that compared to the previous generation process, the 3-nanometer GAA process can deliver a 30% improvement in performance, a 50% reduction in power consumption, and a 45% reduction in chip size. In the report, Samsung also claimed that it is more energy-efficient compared to FinFET technology, which is utilized by the TSMC’s 3-nanometer process.

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(Photo credit: Samsung)

According to Taiwan’s Media TechNews, Taiwan Semiconductor Manufacturing Company (TSMC) is actively building its 2-nanometer (2nm) fab, with significant investments in the northern, central, and southern regions of Taiwan. These investments include the Baoshan fab in Hsinchu, the Central Taiwan Science Park fab, and the Nanzi fab in Kaohsiung. However, the latest supply chain reports suggest that the construction progress of the Baoshan fab is slowing down, potentially affecting the original production schedule. Industry sources speculate that mass production may be delayed until 2026.

In response to these rumors, TSMC stated that the factory construction is currently progressing according to the planned schedule.

TSMC had originally planned to construct Fab 20 at the Baoshan Phase 2 site, with a plan for four 12-inch wafer fabs (P1~P4). Risk Production was scheduled for the second half of 2024, followed by mass production in 2025. Currently, the latest progress indicates that the Hsinchu Science Park Administration has initiated public works for the expansion of the Baoshan Phase 2 project, including infrastructure like surrounding roads and wastewater facilities, and is concurrently handing over the land for TSMC to begin construction.

However, based on supply chain reports, the Baoshan fab construction project is slowing down due to subdued semiconductor demand and uncertainties customer adoption. As a result, the originally scheduled mass production in the second half of 2025 may likely be delayed until 2026.

As for the Kaohsiung fab, it is concurrently starting its 2nm construction, with equipment installation operations originally scheduled to begin just one month after the Baoshan fab. It remains uncertain whether the slowdown in the Baoshan fab construction will have a synchronous impact on the Kaohsiung fab. As for the Taichung fab, it has received approval from the Taichung City government, but construction is expected to commence next year. Some media reports suggest that the Central Taiwan Science Park fab may potentially advance to produce at 1.4nm or even 1nm semiconductor nodes.

Externally, there is speculation that TSMC’s 2nm process will employ nanosheet Gate-All-Around (GAA) transistor architecture for the first time, while Samsung has already adopted GAA technology at the 3nm node. Whether this can give Samsung a competitive edge over TSMC remains to be seen. However, due to the high technical complexity, introducing GAA technology in the early stages of development may face significant yield issues.

What is GAA, and how does it differ from the past FinFET technology?

Based on transistor structure, electrons enter from the source and move towards the drain, with their passage controlled by a metal gate (depicted in green). However, as chip miniaturization continues and the line width of the metal gate shrinks, typically below 20 nanometers, electrons may leak, causing electrical leakage and short circuits. This led to the invention of FinFET technology.

(Source: Applied Materials)

FinFET technology involves standing the source and drain regions vertically (depicted in gray), increasing the contact area with the metal gate. This provides strict control over electrons, preventing them from leaking. The vertical structure resembles a fish fin, hence the name “FinFET.”

However, as the technology scales below 3 nanometers, continuing to use FinFET processes may encounter physical limitations, leading to electrical leakage. To address this, fins need to be transitioned from vertical to horizontal, increasing the contact area even further. This results in the concept of “Gate-All-Around Field-Effect Transistor” (GAAFET).

Samsung began researching GAA architecture early and collaborated with IBM and GlobalFoundries to publish related papers in 2017. TSMC is also prepared to employ nanosheet transistor technology when moving to the 2nm node. However, due to the technical challenges of GAA, the development and production timeline may be delayed. Combined with reports of delays in 2nm fab construction, mass production is likely to be postponed until 2026.

TSMC N2 Nanosheet Concept Image. (Source: Screenshot from the video)