TSMC’s fan-out (InFO) packaging process will no longer be exclusively used by Apple. According to a report from Commercial Times, it’s revealed that Google’s self-developed Tensor chips for their phones will switch to TSMC’s 3nm process next year and will also start using InFO packaging.

TSMC developed InFO packaging based on FOWLP (fan-out wafer-level packaging), which gained prominence after being adopted by the A10 processor in the iPhone 7 in 2016.

TSMC indicated that the current InFO_PoP technology has advanced to its ninth generation. Last year, it successfully certified 3nm chips, achieving higher efficiency and lower power consumption for mobile devices. The InFO_PoP technology, which features a backside redistribution layer (RDL), has entered mass production this year.

According to industry sources cited by the Commercial Times, Google will shift to TSMC for the Tensor G5 chips, which will be used in the Pixel 10 series next year. These chips will not only utilize the 3nm process but will also adopt integrated fan-out packaging.

This year’s Tensor G4 chips, set to be announced soon, use Samsung’s FOPLP (fan-out panel-level packaging). Although wafer-level packaging (WLP) is generally considered to have advantages over panel-level packaging (PLP), FOWLP still prevails at this stage due to yield and cost considerations.

TSMC has also begun developing FOPLP technology. Previously, per sources cited by a report from MoneyDJ, TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

Although it is not expected to mature within the next three years, major customers like NVIDIA have partnered with foundry companies to develop new materials. One of TSMC’s major clients has already provided specifications for using glass materials.

Traditionally, chip advancements have been achieved through more advanced process nodes. However, new materials could enable the integration of more transistors on a single chip, achieving the same goal of scaling.

For instance, Intel plans to use glass substrates by 2030, potentially allowing a single chip to house one trillion transistors – 50 times the number in Apple’s A17 Pro processor. This suggests that glass substrates could become a significant milestone in chip development.

Another sources cited by Commercial Times have also indicated that glass substrates are part of the medium- to long-term technological roadmap. They can address challenges in large-size, high-density interconnect substrate development.

Currently, this technology is in the early stages of research and development. Its impact on ABF (Ajinomoto Build-up Film) substrates is expected to become significant in the second half of 2027 or later.

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• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road

(Photo credit: TSMC)

According to a previous report from Nikkei citing sources, TSMC is rumored to be entering the fan-out panel-level packaging sector. As cited in a report from UDN, Intel and Samsung have also announced plans to invest in this area. With TSMC, the leading wafer foundry, joining the fray, the three semiconductor giants are set to compete in fan-out panel-level packaging.

TSMC stated yesterday that the company is closely monitoring the progress and development of advanced packaging technologies, including panel-level packaging technology.

Nikkei reported that in response to future AI demand trends, TSMC is collaborating with equipment and material suppliers to develop new advanced chip packaging technology. This technology uses a rectangular substrate for packaging, replacing the current traditional circular wafer, to accommodate more chipsets on a single wafer. The report further mentioned that TSMC’s research is still in its early stages and might take several years to commercialize, but it represents a significant technological shift.

Reportedly, TSMC previously considered the challenge of using rectangular substrates to be too high, requiring substantial time and effort from both the company and its suppliers, along with upgrades or replacements of many production tools and materials.

Nikkei  also mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

TSMC is expanding its advanced chip packaging capacity, with the expansion of the Taichung plant mainly for NVIDIA, while the Tainan plant is primarily for Amazon and its chip design partner Alchip Technologies.

TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips in two years.

Samsung and Intel have also recognized the aforementioned issues and are investing in next-generation advanced packaging technologies.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

Intel is planning to launch the industry’s first glass substrate solution for next-generation advanced packaging, with mass production scheduled between 2026 and 2030. Intel anticipates that data centers, AI, and graphics processing—markets that require larger volume packaging and higher-speed applications and workloads—will be the first to adopt this technology.

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• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] Samsung Reportedly Targets Q4 Trial Production of SiP Glass Substrate, Competing with Intel in the Advanced Packaging Market

(Photo credit: Intel)

Samsung Electronics is ramping up its entry into the semiconductor glass substrate market by advancing its equipment procurement and installation to September, with trial production slated to begin in the fourth quarter, one quarter earlier than originally planned. According to a report from South Korean media outlet ETNews, Samsung Electronics aims to commence mass production of glass substrates for high-end System-in-Package (SiP) applications starting in 2026.

In order to manufacture highly complex multi-chiplet SiPs, Samsung has decided to expedite the trial production schedule at its Sejong plant in South Korea to gain more expertise in glass substrate manufacturing. Samsung’s competitor, Intel, also plans to offer packaging technology on glass substrates in the future.

Reportedly, Samsung Electronics plans to have all necessary equipment installed on the trial production line by September and commence operations in the fourth quarter. Partners for the trial production line include companies such as Philoptics, Chemtronics, Joongwoo M-Tech, and Germany’s LPKF, which will provide equipment components.

According to a report from Tom’s Hardware, Compared to traditional organic substrates, glass substrates offer significant advantages, including excellent flatness, which enhances exposure and focusing capabilities, as well as outstanding dimensional stability suitable for next-generation chip interconnects with multiple small chips. Additionally, glass substrates exhibit better thermal and mechanical stability, making them suitable for high-temperature durable applications in data centers.

Intel has been developing glass substrates for nearly a decade and plans to introduce commercial products by 2030. Intel believes that the characteristics of glass substrates will significantly increase interconnect density, which is crucial for efficient power transmission and signal routing in advanced SiP technology.

Previously, Intel also elaborated on its progress on the glass-based substrate packaging technology. According to Intel’s previous press release, glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography as well as the dimensional stability needed for extremely tight layer-to-layer interconnect overlay.

As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Furthermore, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

Meanwhile, Absolics, a subsidiary of SKC America, aims to start production of glass substrates for customers as early as the second half of 2024.

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• [News] Samsung Bullish on Glass Substrate Applications, Setting Up Production Line for Mass Production Starting in 2026
• [News] Glass Substrates in Advanced Packaging With Intel Leads, TSMC Quietly Innovates

(Photo credit: Intel)

Samsung, as per a report from the global media outlet wccftech, has decided to enter the next generation of packaging technology by commencing R&D works for the adoption of “Glass Substrate” by 2026.

The report further indicates that Samsung’s preparation to enter the glass substrate industry for advanced packaging is not actually a new endeavor. As several years ago, competitor Intel had already made strides in this area. The commencement of significant production is expected to begin around 2030. In preparation for large-scale production, Intel has already begun establishing production lines in Arizona, investing USD 1 billion.

To address the current market’s capacity gap, Samsung has also initiated plans to commence glass substrate production.

Currently, under the Samsung Group umbrella, Samsung Electronics is in the process of implementing construction plans for production lines and is also conducting research and development on the application of glass substrates in the field of AI chips.

Additionally, Samsung Group is coordinating various departments within its conglomerate, such as Samsung Display, to further ensure the smooth completion of research and development as well as production efforts related to glass substrates.

The report indicates that through the application of advanced packaging technology using glass substrates, there are several advantages over traditional organic substrate packaging techniques, and it can overcome more technical bottlenecks.

For instance, glass substrates can offer higher strength, ensuring greater durability and reliability, as well as higher interconnectivity. Moreover, glass substrates are thinner than typical organic substrates, enabling the linking of more small chips in advanced packaging technology.

Previously, Intel also elaborated on the glass-based substrate packaging technology. According to Intel’s previous press release, glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

However, despite the many application advantages of glass substrates in the current market, the R&D efforts of various companies have encountered difficulties, impacting the market’s application status.

Currently, Samsung Electronics expects to mass-produce glass substrate products in 2026. Whether it can replace traditional organic substrates and advance packaging technology development will be a focal point of market attention.

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• [News] Glass Substrates in Advanced Packaging With Intel Leads, TSMC Quietly Innovates

(Photo credit: Intel)

According to Taiwan’s Business Next, as Moore’s Law gradually reaches its limits, semiconductor manufacturers are transitioning from 2D to 3D chip stacking and packaging to increase transistor counts for improved performance. The final step, “packaging,” has become crucial. In line with this trend, Intel has announced the industry’s first glass-based substrate for advanced packaging, breaking traditional constraints, with mass production expected between 2026 and 2030.

Intel’s glass-based substrate packaging technology has been in development for a decade and was unveiled at the 2023 Innovation Day in Silicon Valley, USA. Intel aims to achieve the goal of accommodating 1 trillion transistors within a single package by 2030 using advanced glass-based packaging.

The rise of the AI wave has driven the demand for accelerated computing, increasing the requirements for chip density. Intel argues that current substrate materials consume more power and are more prone to expansion and warpage compared to glass, which better aligns with future needs. Industry analysts have noted that TSMC also has similar solutions.

According to Intel, Glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

Glass substrates’ tolerance to higher temperatures also offers chip architects flexibility on how to set the design rules for power delivery and signal routing because it gives them the ability to seamlessly integrate optical interconnects, as well as embed inductors and capacitors into the glass at higher temperature processing.

According to a report from China’s Changjiang Securities released in May, the application of glass substrates in advanced packaging has been validated, and glass manufacturer Corning has introduced related products.

On the other hand, in a report by China’s Changjiang Securities released in May, the application of glass substrates in advanced packaging has been validated, with glass manufacturer Corning introducing related products.

(Photo credit: Intel)