HBM4, the sixth generation of HBM, is poised to become the key to breakthroughs in computing power for next-generation CSPs (Cloud Service Providers). According to a report from Commercial Times citing Global Unichip Corp. (GUC), to support the development of HBM4, their semiconductor IP (Intellectual Property) is already prepared and awaiting CSP manufacturers to advance their manufacturing processes.

GUC pointed out that if future clients need to integrate general-purpose HBM4 into ASICs (Application-Specific Integrated Circuits), GUC can provide assistance.

GUC further emphasized that its IP is ready for HBM4 development, waiting for CSPs to advance their manufacturing processes. Currently, the ASICs being mass-produced by CSPs still use HBM2 or HBM2e, while HBM3 is in the R&D stage.

The company candidly acknowledged that it cannot play any role at the moment and needs to wait for CSPs to adopt HBM4 on a large scale, taking cost considerations into account. When that time comes, GUC expects to assist CSPs in designing their solutions.

Currently, SK hynix has the technological capability for the general-purpose base die used in HBM4. However, when moving to more advanced processes like 5nm or beyond, external design service providers will be required.

Industry sources cited by Commercial Times believe that the pace of advancements in computing power is accelerating.

For instance, Google’s sixth-generation TPU, expected to be launched by the end of this year, is already based on TSMC’s 4nm process and designed on the Arm architecture.

Similarly, Meta’s upcoming MTIAv2 is built on TSMC’s 5nm process. The trend toward developing in-house chips is characterized by lower power consumption and larger memory capacities.

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(Photo credit: GUC)

According to a report by the Economic Daily News, TSMC has secured another AI business opportunity. Following its exclusive contract manufacturing of AI chips for tech giants such as NVIDIA and AMD, TSMC, in collaboration with its subsidiary, the ASIC design service provider Global Unichip Corporation (GUC), has reportedly made significant progress in producing essential peripheral components for AI servers, specifically high-bandwidth memory (HBM). Together, they have secured a major order for the foundational base die chips of next-generation HBM4.

TSMC and GUC typically do not comment on order details. SK Hynix, on the other hand,  has clarified in a press release to Bloomberg that it has not signed a contract with GUC for its next-generation AI memory chips, according to the Economic Daily News.

Industry sources cited by the report point out that the strong demand for AI is not only making high-performance computing (HPC) related chips highly sought after, but also driving robust demand for HBM, creating new market opportunities. This surge in demand has attracted major memory manufacturers such as SK Hynix, Samsung, and Micron to actively invest. Under the influence of AI engines, the current production capacity for HBM3 and HBM3e is in a state of supply shortage.

As AI chip manufacturing advances to the 3nm generation next year, the existing HBM3 and HBM3e, limited by capacity and speed constraints, may prevent the new generation of AI chips from reaching their maximum computational power. Consequently, the three major memory manufacturers are unanimously increasing their capital expenditures and starting to invest in the development of next-generation HBM4 products, aiming for mass production by the end of 2025 and large-scale shipments by 2026.

While memory manufacturers are delving into the research and development of next-generation HBM4, the semiconductor standardization organization JEDEC Solid State Technology Association is also busy establishing new standards related to HBM4. It’s also rumored that JEDEC will relax the stacking height limit for HBM4 to 775 micrometers, hinting that the previously required advanced packaging technology using hybrid bonding can be postponed until the next generation of HBM specifications.

Industry sources cited by the report also suggest that the most significant change in HBM4, besides increasing the stacking height to 16 layers of DRAM, will be the addition of a logic IC at the base to enhance bandwidth transmission speed. This logic IC, known as the base die, is expected to be the major innovation in the new generation of HBM4 and possibly a reason for JEDEC’s relaxation of the stacking height limitation.

On the other hand, SK Hynix has announced its collaboration with TSMC to advance HBM4 and capture opportunities in advanced packaging. Industry sources also indicate that GUC has successfully secured the critical design order for SK Hynix’s HBM4 base die.

The design is expected to be finalized as early as next year, with production to be carried out using TSMC’s 12nm and 5nm processes, depending on whether high performance or low power consumption is prioritized.

Reportedly, it’s suggested that SK Hynix’s decision to entrust the base die chip orders to GUC and TSMC is primarily because TSMC currently dominates over 90% of the CoWoS advanced packaging market used in HPC chips.

Read more

• [News] SK Hynix Disclosed Details Regarding HBM4e, Reportedly Integrating Computing and Caching Functionalities
• [News] SK Hynix Partners with TSMC to Strengthen HBM Technological Leadership

(Photo credit: TSMC)