Facing increased market demand and the ongoing recovery of the memory industry, a report from Korean media outlet ETNews has reported that Samsung has confirmed its investment plan for the 6th-Generation DRAM production line at the Pyeongtaek P4 plant, with the goal of starting mass production in June 2025.

Reportedly, the 6th-generation DRAM, known as ‘1c ,’ is a next-generation DRAM utilizing 10nm-class technology. Despite it is said to be a product that has not yet been commercialized in the global semiconductor industry, both Samsung Electronics and SK hynix are already preparing for mass production.

Samsung’s Pyeongtaek P4 is a comprehensive semiconductor production center, divided into four phases.

As per ETNews, Samsung plans to initiate 1c DRAM production by the end of this year. The company is said to be considering launching HBM4 using 1c DRAM in the second half of 2025.

Given that HBM consumes significantly more DRAM than traditional memory, it is speculated by the report that Samsung’s construction of the 1c DRAM production line at the Pyeongtaek P4 plant may also be in preparation for HBM4.

As per TrendForce’s latest report on the memory industry, it’s revealed that DRAM and NAND Flash revenues are expected to see significant increases of 75% and 77%, respectively, in 2024, driven by increased bit demand, an improved supply-demand structure, and the rise of high-value products like HBM.

Furthermore, TrendForce also reports that Samsung’s P4L facility will be the key site for expanding memory capacity starting in 2025, starting with NAND production. Equipment installation for DRAM is expected to begin in mid-2025, with mass production of 1c nanometer DRAM slated to commence in 2026.

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(Photo credit: Samsung)

As the demand for memory chips used in AI remains strong, prompting major memory companies to accelerate their pace on HBM3e and HBM4 qualification, SK hynix CEO Kwak Noh-jung stated on August 7 that driven by the high demand for memory chips like high-bandwidth memory (HBM), the market is expected to stay robust until the first half of 2025, according to a report by the Korea Economic Daily.

However, Kwak noted that the momentum beyond 2H25 “remains to be seen,” indicating that the company needs to study market conditions and the situation of supply and demand before making comments further. SK hynix clarified that was not an indication of a possible downturn.

According to the analysis by TrendForce, HBM’s share of total DRAM bit capacity is estimated to rise from 2% in 2023 to 5% in 2024 and surpass 10% by 2025. In terms of market value, HBM is projected to account for more than 20% of the total DRAM market value starting in 2024, potentially exceeding 30% by 2025.

SK hynix, as the current HBM market leader, said earlier in its earnings call in July that its HBM3e shipment is expected to surpass that of HBM3 in the third quarter, with HBM3e accounting for more than half of the total HBM shipments in 2024. In addition, it expects to begin supplying 12-layer HBM3e products to customers in the fourth quarter.

The report notes that for now, the company’s major focus would be on the sixth-generation HBM chips, HBM4, which is under development in collaboration with foundry giant TSMC. Its 12-layer HBM4 is expected to be launched in the second half of next year, according to the report.

Samsung, on the other hand, had been working since last year to become a supplier of NVIDIA’s HBM3 and HBM3e. In late July, it is said that Samsung’s HBM3 has passed NVIDIA’s qualification, and would be used in the AI giant’s H20, which has been developed for the Chinese market in compliance with U.S. export controls. On August 6, the company denied rumors that its 8-layer HBM3e chips had cleared NVIDIA’s tests.

Notably, per a previous report from the South Korean newspaper Korea Joongang Daily, following Micron’s initiation of mass production of HBM3e in February 2024, it has recently secured an order from NVIDIA for the H200 AI GPU.

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(Photo credit: SK hynix)

Amid the wave of AI applications, the demand for high-performance memory continues to mushroom, with DRAM, represented by HBM, gaining significant traction. Meanwhile, to further meet market demand, memory manufacturers are  poised to embrace a new round of DRAM technological “revolution.”

• 4F Square DRAM being Developed Smoothly

According to a report from Korean media outlet Chosun Biz, Samsung Electronics Vice President Changsik Yoo recently announced that Samsung’s next-generation DRAM technology is progressing well. In addition to the successful mass production of 1b DRAM, the development of 4F Square DRAM technology is also proceeding smoothly, with the initial sample of 4F Square DRAM set to be developed by 2025.

Industry sources cited by WeChat account DRAMeXchange indicate that the early DRAM cell structure was 8F Square, while currently commercialized DRAM mainly uses 6F Square. Compared to these two technologies, 4F Square employs a vertical channel transistor (VCT) structure, which can reduce the chip surface area by 30%.

As the cell area decreases, DRAM density and performance increase. Therefore, driven by applications like AI, 4F Square technology is gradually sought after by major storage manufacturers.

Previously, Samsung stated that many companies are working to transition their technology to 4F Square VCT DRAM, although some challenges need to be overcome, including the development of new materials like oxide channel materials and ferroelectrics.

Industry sources believe that the initial sample of Samsung’s 4F Square DRAM in 2025 might be for internal release. Another semiconductor manufacturer, Tokyo Electron, estimates that DRAM using VCT and 4F Square technology will come out between 2027 and 2028.

Furthermore, earlier media reports mentioned that Samsung plans to apply Hybrid Bonding technology to support the production of 4F Square DRAM. Hybrid Bonding is a next-generation packaging technology referring to vertically stack chips to increase cell density and thus improve performance, which will also exert an influence on the development of HBM4 and 3D DRAM.

• HBM4 on the Horizon

In the era of AI, HBM, particularly HBM3e, has thrived in the memory market, prompting fierce competition among the three major DRAM manufacturers. A new race is now underway, primarily focusing on the next-generation HBM4 technology.

In April of this year, SK Hynix announced a partnership with TSMC to jointly develop HBM4. It is reported that the two companies will first work on performance improvements for the base die fitted at the bottom layer within the HBM package. To focus on the development of next-generation HBM4 technology, Samsung has established a new “HBM Development Team.”

In July, Choi Jang-seok, head of the New Business Planning Group in Samsung Electronics’ memory division, revealed that the company is developing a high-capacity HBM4 memory with a single stack of up to 48GB, expected to go into production next year. Recently, Samsung reportedly plans to use a 4nm advanced process to produce HBM4 logic die. Micron, on the other hand, plans to introduce HBM4 between 2025 and 2027 and transition to HBM4E by 2028.

Aside from manufacturing processes, DRAM manufacturers are actively exploring hybrid bonding technology for future HBM products. Compared to existing bonding processes, hybrid bonding eliminates the need for bumps between DRAM memory layers, instead directly connecting the upper and lower layers, copper to copper. This significantly improves signal transmission speed, better matching the high bandwidth requirements of AI computing.

In April of this year, Korean media outlet The Elec reported that Samsung successfully manufactured a 16-layer stacked HBM3 memory based on hybrid bonding technology, with the memory sample functioning normally. This 16-layer stacked hybrid bonding technology will be used to produce HBM4 at scale in the future. SK Hynix plans to adopt hybrid bonding in its HBM production by 2026. Micron is also developing HBM4 and is considering related technologies, including hybrid bonding, which are all under research at present.

• The Development of 3D DRAM Picks up Steam

3D DRAM (Three-dimensional dynamic random-access memory) represents a new DRAM technology with a novel memory cell structure. Unlike traditional DRAM, which places memory cells horizontally, 3D DRAM vertically stacks memory cells, greatly increasing storage capacity per unit area and improving efficiency. This makes it a key development for the next generation of DRAM.

In the memory market, 3D NAND Flash has already achieved commercial application, while 3D DRAM technology is still under research and development. However, as AI, big data, and other applications enjoy burgeoning growth, the demand for high-capacity, high-performance memory will surge, and 3D DRAM is expected to become a mainstream product in the memory market.

HBM technology has paved the way for the 3D evolution of DRAM, enabling DRAM to transition from traditional 2D to 3D. However, current HBM cannot be considered as true 3D DRAM technology. Samsung’s 4F Square VCT DRAM is closer to the concept of 3D DRAM, but it is not the only direction or goal for 3D DRAM. Memory manufacturers have more ideas and creativity in 3D DRAM.

Samsung plans to achieve the commercialization of 3D DRAM by 2030. In 2024, Samsung showcased two 3D DRAM technologies, including VCT and stacked DRAM. Samsung first introduced VCT technology, then upgraded to stacked DRAM by stacking multiple VCTs together to continuously improve DRAM capacity and performance.

Samsung states that stacked DRAM can fully utilize the Z-axis space, accommodating more memory cells in a smaller area, with a single chip capacity exceeding 100Gb. In May of this year, Samsung noted that it, along with other companies, successfully manufactured 16-layer 3D DRAM, but emphasized that it is not ready for mass production. 3D DRAM is expected to be produced using wafer-to-wafer hybrid bonding technology, and BSPDN (Backside Power Delivery Network) technology is also considered.

Regarding Micron, industry sources cited by DRAMeXchange reveal that Micron has filed for a 3D DRAM patent application different from Samsung’s, aiming to alter the shape of transistors and capacitors without placing cells.

BusinessKorea reported in June that SK Hynix achieved a manufacturing yield of 56.1% for its 5-layer stacked 3D DRAM. This means that out of around 1000 3D DRAMs produced on a single test wafer, about 561 viable devices were manufactured. The experimental 3D DRAM demonstrated characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix disclosed specific numbers and features of its 3D DRAM development.

Besides, American company NEO Semiconductor is also engaging in the development of 3D DRAM. Last year, NEO Semiconductor announced the launch of the world’s first 3D DRAM prototype: 3D X-DRAM. This technology resembles 3D NAND Flash, namely increasing memory capacity by stacking layers, offering high yield, low cost, and remarkably high density.

NEO Semiconductor plans to launch the first generation of 3D X-DRAM in 2025, featuring a 230-layer stack and a core capacity of 128Gb, which is several times higher than the 16Gb capacity of 2D DRAM.

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(Photo credit: SK Hynix)

As per a report from Korea Economic Daily citing unnamed sources on July 15th, Samsung Electronics is preparing to mass-produce the logic die for HBM4 using its advanced 4nm process.

The logic die, situated at the bottom of the chip stack, is a core component of HBM. Memory manufacturers are already capable of producing logic dies for existing products like HBM3e. However, regarding HBM4, the sixth-generation model, with its custom features demanded by customers, requires additional wafer processing steps.

Reportedly, Samsung’s 4nm process, which boasts is said boasting a yield rate exceeding 70%, is one of their flagship technologies. This advanced process is also used in producing the Exynos 2400 processor for their flagship AI smartphone, the Galaxy S24.

An industry source cited by the report further stated that the 4nm process is much costlier than the 7nm and 8nm but significantly better in terms of chip performance and power consumption. Reportedly, Samsung, which manufactures HBM3e with the 10nm process, is looking to take the throne in the HBM sector by applying the 4nm process.

On the other hand, SK Hynix announced its collaboration with TSMC in April 2024. In a statement released on April 19th, SK Hynix stated that the two semiconductor giants will collaborate on developing the 6th generation HBM4 chips, with production scheduled for 2026.

The same report from the Korean Economic Daily also addressed that, Samsung has reportedly deployed employees from its System LSI division to the newly established HBM research team. In response to Samsung’s actions, SK Hynix and TSMC have decided to add the 5nm process in addition to the originally planned 12nm process for producing the logic die of HBM4.

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(Photo credit: Samsung)

As top memory giants and AI chip companies all gear up for the combat of next-gen high bandwidth memory (HBM), JEDEC, the leader in the development of standards for the microelectronics industry, revealed the preliminary specifications of HBM4 last week. According to its press release and a report from Wccftech, HBM4 is poised to deliver substantial memory capacities, with densities up to 32Gb in 16-Hi stacks.

According to JEDEC, HBM4 aims to boost data processing rates while preserving key features such as higher bandwidth, reduced power consumption, and increased capacity per die or stack, which are crucial traits for applications that demand efficient management of large datasets and complex calculations, such as generative AI, high-performance computing, high-end graphics cards, and servers.

According to JEDEC’s preliminary specifications, HBM4 is anticipated to feature a “doubled channel count per stack” compared to HBM3, which indicates a higher utilization area, leading to significantly enhanced performance. It is also worth noting that in order to support device compatibility, the new standard ensures that a single controller can work with both HBM3 and HBM4.

JEDEC notes that HBM4 will specify 24 Gb and 32 Gb layers, offering support for TSV stacks ranging from 4-high to 16-high. The committee has initially agreed on speed bins up to 6.4 Gbps, with ongoing discussions for higher frequencies.

Interestingly enough, JEDEC did not specify how HBM4 integrates memory and logic semiconductors into a single package, which would be one of the major challenges the industry has been eagerly trying to solve.

Earlier in June, NVIDIA announced its next-gen Rubin GPU, targeting to be released in 2026, will feature 8 HBM4, while its Rubin Ultra GPU will come with 12 HBM4 chips.

The roadmaps for memory giants on HBM4 is generally in accordance with NVIDIA’s product pipeline. Samsung, for instance, is said to be developing a large-capacity HBM4 memory with a single stack capacity of 48GB, which is expected to enter production in 2025.

The current HBM market leader, SK hynix, on the other hand, has collaborated with TSMC on the development and production of HBM4, scheduled for mass production in 2026.

Micron has also disclosed its next-generation HBM memory, tentatively named HBM Next. It is expected that HBM Next will offer capacities of 36GB and 64GB, available in various configurations.

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(Photo credit: SK hynix)