According to sources cited by a report from Economic Daily News, TSMC’s A16 advanced process node might not necessarily require ASML’s latest advanced chip manufacturing equipment, the High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV), due to its expensive price.

Per a report from Bloomberg, during a technical symposium in Amsterdam on May 14th, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that while he appreciates the capabilities of High-NA EUV, he finds its price tag to be unlikeable.

As per the same report from Bloomberg, ASML’s new machine is capable of imprinting semiconductors with lines measuring just 8 nanometers in thickness — 1.7 times smaller than the previous generation.

In terms of pricing, this EUV machine is reportedly priced at EUR 350 million (roughly USD 380 million), with a weight equivalent to two Airbus A320 passenger planes, according to Bloomberg.

Dr. Kevin Zhang stated that TSMC’s planned A16 node (scheduled for volume production slightly later in 2026) may not necessarily require the use of ASML’s High NA EUV equipment. Instead, TSMC could continue to rely on its existing, older EUV equipment. “I think at this point, our existing EUV capability should be able to support that,” he expressed.

He further mentioned that the decision to adopt the new ASML technology would depend on where it offers the most economic benefits and the technical balance they can achieve. He declined to disclose when TSMC might purchase High-NA EUV from ASML.

On the other hand, Intel has confirmed in mid-April that it has received and assembled the industry’s first High-NA EUV lithography system, which is expected to be able to print features up to 1.7x smaller than existing EUV tools. This will enable 2D feature scaling, resulting in up to 2.9x more density.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

Read more

• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix
• [News] EUV as a Strategic Asset in the Most Advanced Processes: Progress in Intel/TSMC/Samsung’s Adoptions

(Photo credit: ASML)

TSMC announced during its briefing on the 18th that, due to robust demand in the 2-nanometer market, it plans to add another fab to the initially planned two fabs in Kaohsiung.

The company intends to use the 2-nanometer process for all three fabs in Kaohsiung, in addition to the originally planned 2-nanometer fab in Hsinchu’s Baoshan. Furthermore, the land recently acquired in Hsinchu Science Park will also be designated for a 2-nanometer fab. This reflects the strong preference for the 2-nanometer process among customers and underscores TSMC’s confidence in its in-house 2-nanometer process technology.

According to a report by TechNews following the briefing on the 18th, TSMC’s CFO Wendell Huang, stated in a media gathering that the strong demand in the high-performance computing and smartphone markets prompted the decision to increase the number of fabs in Kaohsiung from the originally planned two to three. Once the three 2-nanometer fabs are in full production, Kaohsiung will become a crucial manufacturing hub for TSMC’s 2-nanometer process.

In addition, with the recent approval from the Ministry of the Interior’s Urban Planning Commission, the land in Hsinchu Science Park designated for TSMC’s use, expected to be available in June 2024, is also being planned for a 2-nanometer fab.

Recent market reports suggest that TSMC, the leading semiconductor foundry, is set to proceed as scheduled with its plan to adopt the GAA (Gate-All-Around) architecture from the 2-nanometer process onward.

The P1 wafer fab in Baoshan, located in the Hsinchu Science Park, is anticipated to begin equipment installation as early as April 2024, while the Kaohsiung fab is projected to commence production using the GAA architecture for the 2-nanometer process technology in 2025.

Furthermore, in response to Intel securing the first High-NA EUV exposure equipment from ASML for its 18A advanced process, TSMC has indicated that it is also planning for High-NA EUV exposure equipment. However, the current timeline anticipates engineering verification of the High-NA EUV exposure equipment in 2024, with gradual integration into the manufacturing process set to follow.

(Image: TSMC)