Amid the rising of emerging applications in the AI market, the booming demands for high-performance computing (HPC), high-bandwidth memory (HBM), CoWoS advanced packaging, and high-performance storage, have energized the wafer foundry industry.

Given the broader applicability of 12-inch wafer in advanced process chips, the global expansion of 12-inch wafer production has accelerated in recent years. Leading companies like TSMC, Intel, UMC, Vanguard International Semiconductor (VIS), SMIC, and Huahong have successively released production capacity.

• VIS’ Singapore 12-Inch Fab Got Approved

On September 4, VIS and NXP jointly announced the approval of their Singapore-based 12-inch wafer fab joint venture by regulatory authorities in Taiwan, Singapore, and other regions.

The joint venture, named VisionPower Semiconductor Manufacturing Company (VSMC), will begin construction of its first 12-inch (300mm) wafer fab in the second half of this year.

VIS estimates that trial production will begin in 2027, with profitability expected by 2029. TSMC will provide technological support, and the market holds a favorable long-term outlook for the company’s operations.

Upon its mass production, both companies may consider building a second fab. Currently, VIS operates five 8-inch fabs located in Taiwan and Singapore. Three of the 8-inch fabs are in Hsinchu, and one in Taoyuan. The average monthly capacity of its 8-inch fabs in 2023 was about 279,000 wafers.

• TSMC Expands Production Worldwide

On August 20, TSMC held a groundbreaking ceremony for its new German fab, ESMC, which is set to begin construction by the end of the year and aims to start production by the end of 2027.

The project involves an investment of over EUR 10 billion and is expected to have a monthly capacity of 40,000 12-inch wafers, utilizing TSMC’s 28/22nm planar CMOS and 16/12nm FinFET process technologies.

In early September, Taiwan’s Ministry of Economic Affairs announced that TSMC plans to build a third fab in Japan to produce advanced semiconductors, with construction expected after 2030.

TSMC’s first fab in Kumamoto, Japan, officially opened on February 24, 2023, and will begin mass production in Q4 this year using 28/22nm and 16/12nm process technologies, with a monthly capacity of 55,000 wafers.

The second fab in Kumamoto is planned, with construction expected to start by the end of this year and operations to begin by the end of 2027, targeting 6/7nm nodes.

Additionally, TSMC’s 2nm fabs in Hsinchu (Fab 20) and Kaohsiung (Fab 22) in Taiwan are scheduled to start mass production next year.

In the U.S., TSMC’s first fab in Arizona is scheduled to begin producing chips using 4nm technology in the first half of 2025. The second fab will produce both 3nm and 2nm chips using next-generation nanosheet transistors, with production starting in 2025.

Plans for a third fab are also underway, with production of chips using 2nm or more advanced processes expected to begin in 2028.

• UMC’s Fab 12i in Singapore has Set Equipment in Place

On May 21, UMC held a ceremony for the settlement of equipment at its expanded Fab 12i in Singapore with the arrival of the first equipment.

UMC has operated 12-inch fabs in Singapore for over 20 years, and in February 2022, it announced the plan to invest USD 5 billion to expand Fab 12i, adding a new 12-inch fab with a monthly capacity of 30,000 wafers, focusing on 22/28nm processes. Mass production is expected by early 2026.

• Toshiba’s 12-Inch Wafer Fab Completed

On May 23, Toshiba Electronic Devices & Memory Corporation announced the completion of its new 300mm power semiconductor manufacturing fab, with a total investment of JPY 100 billion and plans to begin production in March 2025.

The fab will be built in two phases, with the first phase starting production within the 2024 fiscal year. Once fully operational, Toshiba’s power semiconductor capacity will be 2.5 times that of 2021. Equipment installation is underway, with mass production expected in the second half of FY2024.

• Powerchip Begins Construction of Two New 12-Inch Fabs

On March 13, Powerchip held a groundbreaking ceremony for a 12-inch wafer fab in partnership with India’s Tata Group, located in Dholera, Gujarat, with a total investment of INR 910 billion rupees (about USD 11 billion).

The fab will have a monthly capacity of 50,000 wafers and will produce chips using 28nm, 40nm, 55nm, 90nm, and 110nm nodes.

In early May, Powerchip also announced plans for a new 12-inch fab to expand advanced packaging capacity to support growing demand for AI devices. Powerchip’s chairman stated that the company will provide interposers, one of the three components in CoWoS packaging technology.

• Texas Instruments Built Three New 12-Inch Fabs

Texas Instruments is currently expanding its 300mm capacity to meet future demand for analog and embedded processing chips. TI plans to invest USD 30 billion in building up to four interconnected fabs (SM1, SM2, SM3, SM4) in the coming decades.

According to its 2022 roadmap, TI will build six 300mm fabs by 2030, with RFAB2 in Richardson, Texas, and LFAB (acquired from Micron) already starting production in 2022 and 2023, respectively. Two of the Sherman fabs were completed in 2023, with two more planned for 2026-2030.

In addition to the plan mentioned above, TI also announced the plan for a second 300mm fab in Lehi, Utah in February 2023, adjacent to its existing 12-inch fab, with production estimated to begin in 2026, focusing on producing analog and embedded processing chips. These fabs will be combined into one once the construction is completed.

On August 16, Texas Instruments announced that it received USD 1.6 billion in funding from the U.S. CHIPS Act. This funding will be used to build a cleanroom for the SM1 fab and complete the pilot production line, construct a cleanroom for LFAB2 to begin initial production, and build the shell for the SM2 fab.

• Intel Focuses on U.S. Projects in Arizona and Ohio

Intel has disclosed chip expansion plans in multiple regions, including Arizona, New Mexico, Ohio, Oregon, Ireland, Israel, Magdeburg, Malaysia, and Poland. However, due to market challenges and poor financial results, some of Intel’s expansion plans have been delayed.

Currently, Intel is advancing the construction of large semiconductor manufacturing plants in Arizona and Ohio for the production of cutting-edge semiconductors, as well as working on equipment development and advanced packaging projects at smaller facilities in Oregon and New Mexico.

• GlobalFoundries Revved up Investment in the U.S. and Portugal

On February 19, the U.S. government announced a USD 1.5 billion subsidy for GlobalFoundries. According to a preliminary agreement with the U.S. Department of Commerce, GlobalFoundries will establish a new semiconductor manufacturing facility in Malta, New York, and expand its existing Fab 8 plant in the same location.

The facility will leverage manufacturing technology already implemented in GlobalFoundries’ plants in Germany and Singapore to produce automotive chips, effectively introducing mature-node technology into Fab 8.

In February of this year, GlobalFoundries also announced a partnership with Amkor Technology to build a large packaging facility in Portugal.

It plans to transfer the 12-inch wafer-level packaging production line from its Dresden plant to Amkor’s facility in Porto, Portugal, aiming to establish Europe’s first large-scale backend facility. GlobalFoundries will retain ownership of the tools, processes, and IP transferred to Porto.

• China’s 12-Inch Wafer Production Lines Entered New Stages

In China, companies like SMIC, Huahong, CR Micro (Shenzhen), and Zensemi (Guangzhou) are making new progresses in 12-inch wafer production.

SMIC expects its monthly 12-inch wafer capacity to increase by 60,000 by the end of the year.

Huahong is speeding up the construction of its new 12-inch fab in Wuxi, with the first lithography machine installed on August 22, aiming for production in 1Q24.

CR Micro’s 12-inch fab in Shenzhen has entered the stage of equipment installation and debugging, with production expected to start in late 2024.

Zensemi’s 12-inch wafer manufacturing production line has went into production.

Read more

• [News] Wafer Foundry Market Shows Signs of Recovery
• [News] Two Contrasting Trends Emerge in Wafer Foundry Industry

(Photo credit: TSMC)

Amid the advancement of emerging applications such as Artificial Intelligence (AI), High-Performance Computing (HPC), data center, and autonomous vehicle, fan-out panel-level packaging (FOPLP) technology has successfully garnered industry attention due to its advantages in significantly improving computing power, reducing latency, and increasing bandwidth. As a result, more manufacturers are entering this field.

Recently, semiconductor equipment manufacturer ACM Research Shanghai introduced the Ultra ECP ap-p panel-level electroplating equipment for FOPLP.

Prior to this, ACM has launched the Ultra C vac-p negative pressure cleaning equipment designed for fan-out panel-level packaging applications, signaling that ACM has successfully entered the high-growth FOPLP market.

It is worth mentioning that since the second quarter of this year, chip manufacturers like AMD have actively approached TSMC and professional OSAT (Outsourced Semiconductor Assembly and Test) companies to promote chip packaging using FOPLP technology, further increasing industry focus on FOPLP.

In fact, advanced packaging has an increasing demand for low-latency, high-bandwidth, and cost-effective semiconductor chips, and FOPLP offers high bandwidth and high-density chip interconnects, making it a technology with higher potential.

FOPLP is a process performed on larger square substrates, allowing multiple chips, passive components, and interconnects to be integrated into a single package on a panel, offering greater flexibility, scalability, and cost effectiveness.

By redistributing chips on larger rectangular panels, FOPLP largely reduces the costs of packaging large GPU and high-density, high-bandwidth memory (HBM).

It is reported that the utilization rate of traditional silicon wafers is less than 85%, while that of panels exceeds 95%. The effective area of a 600×600 mm panel is 5.7 times that of a 300 mm traditional silicon wafer, with overall panel cost expected to decrease by 66%.

The increase in area utilization leads to higher capacity, greater flexibility in AI chip design, and significant cost reduction.

Currently, major players in the FOPLP advanced packaging field include Powertech Technology, ASE Group, SPIL, TSMC, Innolux, JSnepes, and Samsung Electro-Mechanics.

TrendForce points out that FOPLP technology presents advantages and disadvantages, facing both opportunities and challenges. Its main strengths are lower unit cost and larger package size, but as its technology and equipment systems are still developing, the commercialization process is highly uncertain.

It is estimated that the mass production timeline for FOPLP in consumer IC and AI GPU may fall between the second half of 2024 to 2026, and 2027-2028, respectively.

Read more

• [News] Innolux Targets to Begin FOPLP Mass Production by Year-End
• [News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road 

(Photo credit: ACMR)

According to a report from Tom’s Hardware citing industry sources, it’s indicated that Chinese memory giant ChangXin Memory Technologies (CXMT) has started mass production of HBM2. If confirmed, this is approximately two years ahead of the expected timeline, although the yield rate for HBM2 is still uncertain.

Earlier, Nikkei once reported that CXMT had begun procuring equipment necessary for HBM production, estimating it would take one to two years to achieve mass production. Currently, CXMT has ordered equipment from suppliers in the U.S. and Japan, with American companies Applied Materials and Lam Research having received export licenses.

Reportedly, HBM2 has a per-pin data transfer rate of approximately 2 GT/s to 3.2 GT/s. Producing HBM2 does not require the latest lithography techniques but does demand enough manufacturing capacity.

The process involves using through-silicon vias (TSV) to vertically connect memory components, which is rather complex. However, packaging the HBM KGSD (known good stack die) modules is still less intricate than manufacturing traditional DRAM devices using a 10nm process.

CXMT’s DRAM technology is said to be lagging behind that of Micron, Samsung, and SK hynix. These three companies have already started mass production of HBM3 and HBM3e and are preparing to advance to HBM4 in the coming years.

There also are reports indicating that Huawei, the Chinese tech giant subject to US sanctions, looks to collaborate with other local companies to produce HBM2 by 2026. Per a previous report from The Information, a group led by Huawei aimed at producing HBM includes Fujian Jinhua Integrated Circuit.

Moreover, since Huawei’s Ascend 910 series processors use HBM2, it has made HBM2 a crucial technology for advanced AI and HPC processors in China. Therefore, local manufacturing of HBM2 is a significant milestone for the country.

Read more

• [News] Bypassing U.S. Restrictions? CXMT Showcases GAA Technology for 3nm Chips
• [News] Progress Made in Chinese Consortium’s Development of HBM, Reportedly Targeting HBM2 Production by 2026

(Photo credit: CXMT)

On July 30, 2024, SK hynix announced the launch of next-generation memory product, GDDR7, with the world’s highest performance.

SK hynix explained that GDDR is characterized by the performance specifically designed for graphic processing and high-speed property, which has gaining an increasingly more traction from global AI application customers. In response to this trend, the company completed the development of the latest GDDR7 specifications in March this year, which was now officially launched and will achieve mass production in the third quarter of this year.

SK hynix’s GDDR7 features an operating speed of up to 32Gbps (32 gigabytes per second), which represents an increase of more than 60% compared to the previous generation, and can stand at 40Gbps depending on the usage environment. Built on the latest graphics card, it can support data processing speed of over 1.5TB per second, equivalent to processing 300 FHD (5GB) movies in one second.

In addition to providing faster speeds, GDDR7 boasts an energy efficiency 50% higher than the previous generation. To address chip heating issue caused by ultra-high-speed data processing, SK hynix adopted new packaging technology in the development of this product.

SK hynix’s technical team maintained the product size while increasing the heat-dissipating layers in the packaging substrate from four to six and used highly thermally conductive epoxy molding compound (EMC) in the packaging materials. As a result, the technical team successfully reduced the thermal resistance of the product by 74% compared to the previous generation.

Lee Sang-kwon, Vice President of SK hynix DRAM PP&E, said that SK hynix’s GDDR7 has achieved the highest performance of existing memory chips with excellent speed and energy efficiency, and its applications will expand from high-performance 3D graphics to AI, HPC, and autonomous driving.

Through this product, the company will further strengthen its high-end memory product line while developing into the most trustworthy AI memory solution company for customers.

Read more

• [News] GDDR7 Emerging as a New Driver for Memory Industry
• [News] SK hynix to Kick off Mass Production for GDDR7 in Q4 2024

(Photo credit: SK hynix)

In the face of adversities within the autonomous vehicle market, car manufacturers are not hitting the brakes. Rather, they’re zeroing in, adopting more focused and streamlined strategies, deeply rooted in core technologies.

Eager to expedite the mass-scale rollout of Robotaxis, Tesla recently announced an acceleration in the development of their Dojo supercomputer. They are now committing an investment of $1 billion and set to have 100,000 NVIDIA A100 GPUs ready by early 2024, potentially placing them among the top five global computing powerhouses.

While Tesla already boasts a supercomputer built on NVIDIA GPUs, they’re still passionate about crafting a highly efficient one in-house. This move signifies that computational capability is becoming an essential arsenal for automakers, reflecting the importance of mastering R&D in this regard.

HPC Fosters Collaboration in the Car Ecosystem

According to forecasts from TrendForce, the global high-performance computing(HPC) market could touch $42.6 billion by 2023, further expanding to $56.8 billion by 2027 with an annual growth rate of over 7%. And it is highly believed that the automotive sector is anticipated to be the primary force propelling this growth.

Feeling the heat of industry upgrades, major automakers like BMW, Continental, General Motors, and Toyota aren’t just investing in high-performance computing systems; they’re also forging deep ties with ecosystem partners, enhancing cloud, edge, chip design, and manufacturing technologies.

For example, BMW, who’s currently joining forces with EcoDataCenter, is currently seeking to extend its high-performance computing footprint, aiming to elevate their autonomous driving and driver-assist systems.

On another front, Continental, the leading tier-1 supplier, is betting on its cross-domain integration and scalable CAEdge (Car Edge framework). Set to debut in the first half of 2023, this solution for smart cockpits offers automakers a much more flexible development environment.

In-house Tech Driving Towards Level 3 and Beyond

To successfully roll out autonomous driving on a grand scale, three pillars are paramount: extensive real-world data, neural network training, and in-vehicle hardware/software. None can be overlooked, thereby prompting many automakers and Tier 1 enterprises to double down on their tech blueprints.

Tesla has already made significant strides in various related products. Beyond their supercomputer plan, their repertoire includes the D1 chip, Full Self-Driving (FSD) computation, multi-camera neural networks, and automated tagging, with inter-platform data serving as the backbone for their supercomputer’s operations.

In a similar vein, General Motors’ subsidiary, Cruise, while being mindful of cost considerations, is gradually phasing out NVIDIA GPUs, opting instead to develop custom ASIC chips to power its vehicles.

Another front-runner, Valeo, unveiled their Scala 3 in the first half of 2023, nudging LiDAR technology closer to Level 3, and laying a foundation for robotaxi(Level 4) deployment.

All this paints a picture – even with a subdued auto market, car manufacturers’ commitment to autonomous tech R&D hasn’t waned. In the long run, those who steadfastly stick to their tech strategies and nimbly adjust to market fluctuations are poised to lead the next market resurgence, becoming beacons in the industry.

For more information on reports and market data from TrendForce’s Department of Semiconductor Research, please click here, or email Ms. Latte Chung from the Sales Department at lattechung@trendforce.com

(Photo credit: Tesla)