Global semiconductor giants are concentrating their R&D efforts on advanced packaging technologies to drive performance enhancements. According to a report from Commercial Times, as packaging technology progresses from 2.5D to 3D, chip stacking technologies have become a showcase for the competitive prowess of major companies.

“Hybrid Bonding” is seen as the key technology for future chip connections. In addition to international companies like Applied Materials and Besi actively positioning themselves, Taiwanese companies led by TSMC, including Gallant Micro, MPI Corporation, E&R Engineering Corporation, C SUN, Saultech, and Grand Process Technology, are also developing and seizing opportunities in Hybrid Bonding.

The report also cited industry sources, pointing out that Grand Process Technology has been supplying TSMC since the inception of InFO (Integrated Fan-Out Packaging). It is revealed that Grand Process Technology is also actively participating in future SoIC (System on Integrated Chips) advanced packaging, focusing on wafer cleaning and photoresist removal in etching processes.

It is indicated by the report that Grand Process Technology’s capacity will be operating at full speed until the first quarter of next year, with lead times extended to nine months. Last year’s orders are currently being installed gradually, with most concentrated on advanced packaging.

Semiconductor equipment manufacturer C SUN and its investment company Gallant Micro are currently investing in Hybrid Bonding-related equipment. C SUN primarily focuses on developing the best solutions for permanent bonding to enhance yield rates. Meanwhile, Gallant Micro leverages its relative advantage in chip sorting machines within its product line.

MPI Corporation, a testing interface vendor, has also entered the initial stages of inspection and analysis for Hybrid Bonding processes. Development of related products is nearing completion.

E&R Engineering Corporation also emphasizes that its top-tier plasma cleaning equipment is currently aimed at achieving high cleanliness of bonding surfaces to enhance adhesion.

Saultech Technology holds a positive outlook on the future market trends of Hybrid Bonding as well. The company has introduced equipment that corresponds to both Hybrid Bonding and Fan-Out technologies. Saultech has independently developed key technologies including bonding and die cleaning processes.

Read more

• [News] Samsung and SK hynix to Implement Hybrid Bonding with 3D DRAM
• [News] The HBM4 Battle Begins! Memory Stacking Challenges Remain, Hybrid Bonding as the Key Breakthrough
  

(Photo credit: Applied Materials)

According to the latest report by TheElec, though Samsung has been using thermal compression (TC) bonding until its 12-stack HBM, the company now confirms its belief that hybrid bonding is necessary for manufacturing 16-stack HBM.

Regarding its future HBM roadmap, Samsung reportedly plans to produce its HBM4 sample in 2025, which will mostly be 16 stacks, with mass production slated for 2026, the report noted. According to TheElec, earlier in April, Samsung used hybrid bonding equipment from its subsidiary, Semes, to produce a 16-stack HBM sample, of which it indicated to operate normally.

Citing information Samsung revealed during the 2024 IEEE 74th Electronic Components and Technology Conference last month, TheElec learned that Samsung considered hybrid bonding essential for HBM with 16 stacks and above.

According to the report, Samsung has been using thermal compression (TC) bonding until its 12-stack HBM. However, now it emphasized on hybrid bonding’s ability to reduce height, which would be indispensable for 16-stack HBM. By further narrowing the gap between chips, 17 chips (one base die and 16 core dies) can be fitted within a 775-micrometer form factor.

According to an earlier report from TechNews, Samsung and Micron use TC-NCF technology (thermal compression with non-conductive film) on HBM production, which requires high temperatures and high pressure to solidify materials before melting them, followed by cleaning. The industry has relied on traditional copper micro bumps as the interconnect scheme for packages, while their sizes pose challenges when trying to allow more chips to be stacked at a lower height.

Samsung stated that though making the core die as thin as possible or reducing the bump pitch could help, these methods have reached their limits. Sources cited by the Elec mentioned that it is very challenging to make the core die thinner than 30 micrometers. Also, using bumps to connect the chips has limitations due to the volume of the bumps. Thus, hybrid bonding technology may emerge as a promising solution.

While the current technology uses micro bump materials to connect DRAM modules, hybrid bonding, which could stack chips veritically by using through-silicon-via (TSV), can eliminate the need for micro bumps, significantly reducing chip thickness.

On the other hand, according to another report by Business Korea, SK hynix has shown its confidence in the HBM produced with Mass Reflow-Molded Underfill (MR-MUF) technology. MR-MUF technology attaches semiconductor chips to circuits, using EMC (liquid epoxy molding compound) to fill gaps between chips or between chips and bumps during stacking.

SK hynix reportedly plans to begin mass production of 16-layer HBM4 memory in 2026, and the memory heavyweight is currently researching hybrid bonding and MR-MUF for HBM4, but yield rates are not yet high, the report said.

Read more

• [News] The HBM4 Battle Begins! Memory Stacking Challenges Remain, Hybrid Bonding as the Key Breakthrough
• [News] Jensen Huang Confirms NVIDIA Approaches Certification of Samsung’s HBM Chips

(Photo credit: Samsung)

At TSMC’s 2024 Technology Symposium in late May, Kevin Zhang, TSMC Senior Vice President of Business Development, has shared the company’s latest development on advanced packaging. This article recaps the highlights in the forum, featuring TSMC’s breakthroughs regarding advanced packaging.

Advanced Packaging

SoW (System-on-Wafer Integration Technology)

SoW adopts TSMC’s InFO and CoWoS packaging technologies to integrate logic dies and HBM memory on the wafer. By doing so, TSMC aims to enhance performance and speed not just at the chip level, but the system level as well.

Currently, TSMC’s system-on-wafer manufactured with InFO technology has entered mass production. Afterwards, the company plans to develop and launch SOW using CoWoS technology to integrate SoC or SoIC, HBM, and other components together.

TSMC eyes its System-on-Wafer manufactured with the CoWoS technology to enter mass production in 2027, while its target applications would include AI and HPC, expanding the computational power needed for data centers of the next generation.

3DFabric

TSMC’s 3DFabric technology family includes three major platforms: SoIC, CoWoS, and InFO, encompassing both 2D and 3D front-end and back-end interconnect technologies.

SoIC

The SoIC platform offers two stacking solutions: SoIC-P (Bumped) and SoIC-X (Bumpless). The first solution, SoIC-P, is a micro-bump stacking solution suitable for cost-effective applications such as mobile devices.

The other solution, SoIC-X, adopts Hybrid Bonding, which is ideal for HPC and AI demands. The advantage of this solution is that the pitch between contacts can be reduced to a few micrometers (µm), increasing the interconnect interface between two chips while achieving a new level of interconnect density.

TSMC’s current bond pitch density with Hybrid Bonding has been reduced to 6 micrometers, and it aims to further reduce it 2 to 3 micrometers. In the meantime, the company has been advancing micro-bump technology, currently at over 30 micrometers, with the future goal of reducing it to the teens.

TSMC revealed that customer demand for SoIC-X technology has been increasing, with 30 customer design tape-outs expected by the end of 2026.

CoWoS / InFO

The CoWoS advanced packaging family includes three members: CoWoS-S, CoWoS-L, and CoWoS-R. The three platforms can mainly be differentiated by their intermediate layer materials, which may also affect the cost. In other words, CoWoS-S utilizes silicon interposer, CoWoS-L uses LSI (Local Silicon Interconnect), while CoWoS-R uses RDL (Redistribution Layer) wiring to connect small chips.

Depending on product requirements, SoIC chips can be integrated with either CoWoS or InFO. AMD’s MI300A / MI300 X is the first product to adopt SoIC-X and CoWoS technology.

One of the most well-known product which adopts TSMC’s CoWoS-L technology would be NVIDIA’s Blackwell AI accelerator, which integrates two SoCs using 5nm with eight HBM into one module.

Moreover, TSMC’s CoWoS technology integrates advanced SoCs/SoICs with HBM to meet the requirements of AI chips. Its SoIC has entered mass production through the CoWoS-S platform. Going forward, TSMC plans to develop a SoIC chip with an eight-time mask size (using the A16 process) and a CoWoS solution with 12 HBM stacks. This updated version is expected to enter mass production in 2027.

(Photo credit: TSMC)