As TSMC and other major chip manufacturers compete for AI business opportunities, chip production capacity is unable to keep up with demand. Industry sources cited in a report from NIKKEI claimed that the slow expansion of high-end chip production capacity is due to different packaging and testing technologies used by various companies and calls for the industry to standardize as soon as possible.

Jim Hamajima, President of the Japan office of the Semiconductor Equipment and Materials International (SEMI), recently stated in an interview with NIKKEI that leading chip manufacturers like Intel and TSMC should adopt international standards for back-end processes to effectively and quickly increase production capacity.

Hamajima further noted that each company is trying to apply unique solutions in back-end processes, with TSMC and Intel using different technical standards, which leads to inefficiencies.

Semiconductor manufacturing is divided into two major parts: front-end and back-end processes. While the photolithography technology used in front-end processes widely adopts international standards set by SEMI, packaging and testing in back-end processes vary among manufacturers. For example, TSMC uses CoWoS technology for advanced packaging, while Samsung Electronics uses I-Cube technology.

In recent years, chip manufacturers have actively invested in the development of advanced packaging technologies, primarily because front-end processes face technical bottlenecks, making back-end processes the key to gaining a competitive edge.

Hamajima believes that the current state of back-end processes in the semiconductor industry is “Balkanized,” with each company adhering to its own technologies, leading to a fragmented industry. He warns that this issue will start to impact profit margins as more powerful chips are produced in the future.

Hamajima stated that if semiconductor manufacturers adopt standardized automated production technologies and material specifications, it will be easier to acquire manufacturing equipment and upstream material supplies when expanding production capacity.

Hamajima is a director of a recently launched consortium led by Intel and 14 Japanese companies to jointly develop automated systems for back-end processes. The collaborating companies include Japanese companies such as Omron, Yamaha Motor, Resonac, and Shin-Etsu Polymer, a subsidiary of Shin-Etsu Chemical Industry.

Hamajima noted that Japan, with its numerous automation equipment and semiconductor material suppliers, is an ideal location to test international standards for back-end processes.

He also acknowledged that currently, Intel is the only multinational chip manufacturer in the alliance, which might lead to the development of technical standards that favor Intel. However, he emphasized that the alliance welcomes other chip manufacturers to join, and the research outcomes will serve as a reference for future industry standard-setting.

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(Photo credit: TSMC)

As semiconductor process technology nears known physical limits, the spotlight among major industry players is shifting towards the development of advanced packaging. Concurrently, the rise of applications like artificial intelligence and AIGC has propelled the concept of advanced packaging into a new technological wave. In the midst of the semiconductor industry’s global competition, securing more orders has become a core objective for major players.

A Competitive Landscape in Advanced Packaging

The competition in advanced packaging technology is intensifying, with companies pouring substantial investments into the field, resulting in a landscape of vigorous competition. Various packaging technologies have emerged, with notable offerings from industry giants such as TSMC, Intel, and Samsung.

TSMC introduced 3DFabric, an integration of its TSMC-SoIC front-end technology with CoWoS and InFO back-end technologies, providing maximum flexibility for diverse innovative product designs.

Intel, on the other hand, features its 2.5D EMIB and 3D Foveros packaging technologies. EMIB is applied in the connection of logic chips and high-bandwidth memory, as seen in the Intel Xeon Max series and Intel Data Center GPU Max series.

Foveros allows top dies to overcome size limitations and accommodate more top and base dies, connected through copper pillars to reduce potential interference from through-silicon vias (TSVs).

Samsung also exhibits strong competitiveness in advanced packaging, with its 2.5D I-Cube4 and H-Cube, along with 3D X-Cube packaging technologies, achieving breakthroughs in multi-chip interconnects and integration.

Samsung’s I-Cube4, for example, integrates four HBM stack dies and one core compute IC on the silicon interposer layer, while H-Cube enhances packaging area through the stacking of HDI PCBs to accommodate designs with six or more HBM stack dies.

Advantages of the Three Giants

In recent years, the three semiconductor giants have directed substantial capital expenditure towards advanced packaging. Their diverse technological developments and marketing strategies are poised to ignite a global battle in the semiconductor advanced packaging industry.

TSMC holds the advantage with its dominant wafer process technology and an end-to-end comprehensive service approach. Coupled with Taiwan’s robust semiconductor ecosystem, TSMC leads the way in the advanced packaging domain.

Intel, while slightly trailing TSMC in advanced process technology, matches it in advanced packaging capabilities. Emphasizing flexible foundry services, Intel allows clients to mix and match its wafer manufacturing and packaging offerings. With manufacturing facilities scattered worldwide, Intel leverages geographic advantages, particularly in Western countries, to expand capacity and services, leading to anticipated gains in the future.

Samsung, like TSMC, offers end-to-end services, but its packaging technology lags behind TSMC’s. It secures a share in constrained supply situations. Notably, Samsung, in June 2022, was ahead of TSMC in unveiling the innovative GAA 3nm process, and is poised to combine it with 3D packaging technology, potentially marking a pivotal point in the next semiconductor generation.

With semiconductor technology’s continuous evolution and surging market demand, the competition among the three giants in advanced packaging will remain fierce. While wafer fabs currently prioritize processes, the next three to five years are expected to witness a gradual shift towards advanced packaging. Different packaging technologies and marketing strategies will ultimately determine companies’ positions and influence in the market.

(Photo credit: TSMC)

Read more:

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• ASE, Amkor, UMC and Samsung Getting a Slice of the CoWoS Market from AI Chips, Challenging TSMC