TSMC, along with research teams like imec, continues to push the boundaries in pursuit of optimal solutions for achieving high bandwidth and low power consumption on the same chip area.

As per a report from Commercial Times, Imec has even mapped out a blueprint for the Angstrom era, with the potential to surpass the A1 threshold by 2040. They have also revealed that the A14 node will require the adoption of High-NA EUV (Extreme Ultraviolet Lithography with High Numerical Aperture), reportedly hinting that TSMC’s adoption of High-NA EUV is inevitable.

Per another report from the Economic Daily News, Luc Van den hove, President and CEO of imec, presented imec’s latest technological roadmap at the ITF Taiwan 2024 forum. He outlined plans to advance to the 2nm node by 2025, enter the angstrom era with the A14 process by 2027, and reach the A2 process by 2037.

He also explained the changes in imec’s transistor architecture, stating that the 2nm process will transition from FinFET to Nanosheet architecture, while the A7 process will further shift to complementary FET (CFET) architecture.

This, per Commercial Times’ report, hints that TSMC’s adoption is only a matter of time. TSMC emphasized that whenever new structures and tools, such as High-NA EUV, emerge, they carefully evaluate their maturity, costs, schedules, and feasibility.

Min Cao, Vice President of R&D at TSMC, pointed out that the performance, power, and area (PPA) gains from field-effect transistors (FETs) are diminishing. To sustain high growth, TSMC does not rule out the development of emerging materials.

He further expressed optimism about the significant growth wave driven by artificial intelligence, noting that the complexity of AI models and computational power is expected to grow exponentially.

Min Cao noted that the automotive sector will soon adopt 3nm and 5nm chips, and TSMC will be able to support the advancement of autonomous driving. He estimated that the semiconductor market will reach a scale of USD 1 trillion by 2030.

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(Photo credit: TSMC)

According to a report from UDN, TSMC held a groundbreaking ceremony yesterday for its Dresden, Germany plant, offering a significant boost to the EU’s efforts to stabilize its chip supply.

TSMC Chairman C.C. Wei led a team of top executives at the event, joined by key officials including German Chancellor Olaf Scholz. European Commission President Ursula von der Leyen also attended, bringing with her the announcement that the EU has approved a EUR 5 billion subsidy for the Dresden plant.

TSMC announced last August that it would partner with Bosch, Infineon, and NXP Semiconductors to establish the European Semiconductor Manufacturing Company (ESMC) in Germany.

The joint venture will construct a 12-inch wafer plant, with TSMC holding a 70% stake, while Bosch, Infineon, and NXP each hold 10%. Construction is planned to start in the second half of this year, with mass production expected by the end of 2027.

The planned fab is expected to have a monthly production capacity of 40,000 12-inch wafers on TSMC’s 28/22 nanometer planar CMOS and 16/12 nanometer FinFET process technology.  TSMC will be responsible for the plant’s operations.

Following the U.S.-China tech war, the EU passed the “Chips Act” to fully support the development of the semiconductor industry, attracting key investments from companies such as TSMC, Intel, Belgium’s IMEC, GlobalFoundries, and GlobalWafers, all of which sought subsidies for their new European operations.

TSMC’s joint venture proposal, exceeding EUR 10 billion, stands as the largest global direct investment in Saxony’s history.

When C.C. Wei took the stage, he began by thanking the German government. He revealed that when he first met with the German Chancellor, he had prepared a polite speech to decline the offer of building a plant in Germany.

However, when the Chancellor mentioned that a budget had already been reserved for TSMC, Wei eventually found himself agreeing to the project.

C.C. Wei further highlighted that TSMC’s total investment in the German plant exceeds EUR 10 billion and is expected to create around 2,000 jobs.

He explained that the decision to locate the plant in Dresden was due to its proximity to TSMC’s customers and access to a large pool of talented individuals. Wei also pledged to continue recruiting and nurturing talent in the region, with the goal of making ESMC the most important semiconductor manufacturing hub in Europe.

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• [News] TSMC Maintains Overseas Expansion Strategy, Unfazed by Geopolitical Disruptions
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(Photo credit: TSMC)

On June 18th, Belgium’s microelectronics research center IMEC showcased the first CMOS CFET device featuring stacked bottom and top source/drain contacts at the 2024 IEEE VLSI Technology and Circuits Symposium (2024 VLSI). Although the results were achieved using front-side lithography techniques for both contacts, imec also demonstrated the feasibility of transferring the bottom contacts to the back side of the wafer, which potentially increases the survival rate of top devices from 11% to 79%.

IMEC explained that their logic technology roadmap envisions the introduction of Complementary Field-Effect Transistor (CFET) technology into device architectures at the A7 node. Paired with advanced wiring technologies, CFET is expected to reduce the standard cell height from 5T to 4T or even lower without sacrificing performance. Among the different approaches to integrating vertically stacked nMOS and pMOS structures, monolithic integration is considered the least disruptive compared to existing nanosheet process flows.

At VLSI Symposium 2024, IMEC demonstrated for the first time a functional monolithic CMOS CFET device with both top and bottom contacts. The device features a gate length of 18nm, a gate pitch of 60nm, and a vertical distance of 50nm between the n-type and p-type. The process flow IMEC’s proposed includes two CFET-specific modules: Middle Dielectric Isolation (MDI) and stacked bottom and top contacts.

MDI is a module pioneered by IMEC to isolate the top and bottom gates and to differentiate threshold voltage settings between n-type and p-type devices. Based on modifications to the “active” multilayer Si/SiGe stack in CFET, MDI module allows for the co-integration of internal spacers—a feature unique to nanosheets that isolates the gate from the source/drain.

“We obtained the best results in terms of process control with an MDI-first approach, i.e., before source/drain recess – the step where nanosheets and MDI are ‘cleaved’ to gain access to the channel sidewalls and start source/drain epi. An innovative source/drain recess etch with ‘in-situ capping’ enables MDI-first by protecting the gate hardmask/gate spacer during the source/drain recess.” stated Naoto Horiguchi, IMEC’s CMOS device technology director, as per a report from IMEC.

The second critical module is the formation of stacked source/drain bottom and top contacts, vertically separated by dielectric isolation. Key steps involve bottom contact metal filling and etching, followed by dielectric filling and etching—all completed within the confined space of the MDI stack.

Naoto Horiguchi noted that developing bottom contacts from the front side encountered many challenges, which potentially impacts bottom contact resistance and limits the process window for top devices. At VLSI 2024, IMEC indicated that despite additional processes like wafer bonding and thinning, this design is proved feasible, making the backside bottom contact structure an attractive option for the industry. Currently, research is underway to determine the optimal contact wiring method.

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• [News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

(Photo credit: IMEC)

Belgium-based IMEC Microelectronics Research Center has announced the leading role in establishing the NanoIC pilot line project, for which it has received a total of EUR 2.5 billion from public and corporate donations.

As one of the four advanced semiconductor pilot line projects designated by the European Chips Joint Undertaking (Chips JU), the NanoIC pilot line is to bridge the technology gap between the lab and the fab, accelerating the development, design, and testing of proof-of-concept products through small-scale production.

According to the European Chips Act, which has a total budget of EUR 15.8 billion by 2030, the “European Chips Initiative” is regarded as a key part. This initiative aims to significantly enhance advanced chip technologies and innovation. The European Chips Initiative will gather EU, member states, and resources from the stakeholders from third-party countries related to EU programs, which is expected to be driven by the Chips Joint Undertaking (Chips JU).

In addition to spearheading the NanoIC pilot line project, IMEC will also be a part of two other projects: the advanced FD-SOI process pilot line and the advanced heterogeneous system integration pilot line. The NanoIC pilot line will focus on developing sub-2nm process SoC, providing prototype development PDK to participants from academia to industry, thereby reducing the risk of chip R&D and improving development efficiency.

Of the EUR 2.5 billion in funding, EUR 1.4 billion comes from Chips JU and the Belgian government, while the remaining EUR 1.1 billion comes from partners such as  ASML. IMEC President and CEO Luc Van den hove stated that the support from the EU, the Belgian government, and corporate partners will enable IMEC to maintain a top position and better align with market demands.

This investment will double output and learning speed, accelerate the pace of innovation, strengthen the European chip ecosystem, and hence promote economic growth in Europe.

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(Photo credit: IMEC)