While NVIDIA is likely to face accusations from the French antitrust regulators, the Non-NVIDIA Alliance like the UALink (Ultra Accelerator Link) Alliance and the UXL Foundation are reportedly launching a counterattack, significantly increasing their efforts in developing specialized ASICs.

According to a report from Commercial Times, relevant semiconductor intellectual property (IP) is expected to be widely adopted. The sources cited by the report point out that Taiwanese manufacturers, benefiting from their leading position in wafer foundry and comprehensive ASIC and IP layout, are poised to capitalize on the rise of the Non-NVIDIA Alliance.

The report further cites sources, indicating that major Taiwanese ASIC manufacturers such as Global Unichip, Faraday Technology, and Progate Group Corporation (PGC), along with silicon IP companies M31 Technology Corporation, eMemory, and the Egis Technology Group, are actively expanding in this field.

In order to challenge NVIDIA’s dominance in the market, UALink (Ultra Accelerator Link) Alliance, led by tech giants such Intel and AMD, was formed in May. The alliance aims to establish a new standard for AI accelerator links, aiming to challenge NVIDIA’s  NVLink.

Furthermore, the UXL Foundation’s Open Source Software Project, supported by tech giants Qualcomm, Google, and Intel, is said to be looking to rival NVIDIA’s CUDA software. By providing alternative software solutions, it aims to diminsh NVIDIA’s dominance in the AI field.

Semiconductor industry sources cited in the same report also note that CSPs are accelerating the development of their own chips, with Taiwanese manufacturers actively entering the market.

Although Broadcom and Marvell currently offer diversified design services, Taiwanese manufacturers have an advantage due to the tightly-knit semiconductor supply chain. This enables complete solutions for both chip manufacturing and packaging within Taiwan, giving them a strategic edge over competitors by being close to both the market and factories, thereby enhancing their position in the ASIC sector.

Global Unichip and PGC leverage TSMC as a strong ally. Reportedly, Global Unichip holds AI-related ASIC orders from Microsoft and is gradually finalizing collaborations with major South Korean companies, with business operations expected to improve in the second half of the year.

On the other hand, Faraday Technology closely collaborates with Intel, developing SoCs using Intel’s A18 process. Meanwhile, industry sources cited by the report suggest that Intel’s Gaudi series AI chips might seek collaboration opportunities beyond just working with Alchip.

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• [News] Novatek, a Major Driver IC Manufacturer, Reportedly Eyes Entry into ASIC and Silicon IP Battlefields

(Photo credit: Shutterstock)

Semiconductor equipment giant ASML plans to launch Hyper-NA Extreme Ultraviolet (EUV) machines by 2030, signaling the advent of the Angstrom era for semiconductor processes below 1 nanometer. However, according to a report from The Chosun Daily, the high cost of this equipment may cause TSMC, Samsung, and Intel to hesitate.

Reportedly, it’s said that ASML introduced a higher numerical aperture (high-NA) EUV machine last year, which outperforms existing EUV technology. Now, ASML is rumored to release the Hyper-NA EUV for sub-1nm processes by 2030. This development brings up significant strategic considerations for TSMC, Samsung, and Intel due to the substantial expense involved in acquiring such advanced equipment.

According to the report, currently, each EUV machine costs approximately USD 181 million. The new generation high-NA EUV machines cost from USD 290 million to USD 362 million per unit, while the expected cost for Hyper-NA EUV could exceed USD 724 million, namely, about twice the price of the previous generation.

The same report further points out that TSMC plans to maximize the capabilities of its existing EUV equipment and utilize them through multi-patterning techniques. Simultaneously, the company is evaluating the scale at which additional equipment may be introduced.

A source cited in the report mentioned that though TSMC adopted EUV technology after Samsung, it has managed to mitigate the investment burden of adopting new equipment by upgrading existing tools and employing multi-patterning techniques effectively.

The same source also indicated that TSMC is particularly interested in multi-patterning techniques. By leveraging its extensive expertise and existing EUV infrastructure, TSMC has developed multi-patterning processes, aiming to delay the adoption of high-NA and Hyper-NA EUV as much as possible.

TSMC has openly expressed concerns about the high cost of the new generation high-NA EUV machines. TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, has indicated that the development of 1.6 nanometer processes may not necessarily require high-NA technology.

Zhang further mentioned that the decision to adopt the new ASML technology would depend on where it offers the most economic benefits and the technical balance they can achieve. He declined to disclose when TSMC might purchase High-NA EUV from ASML. 

As per the same report, Samsung is also considering the adoption of high-NA equipment but is adjusting its long-term roadmap with the emergence of Hyper-NA. According to another source cited by the report, it claimed that choosing high-NA now may not be the best option for long-term plans that involve processes below 1 nanometer.

The source continued that given the emergence of Hyper-NA, one approach might be to maximize the use of existing EUV and skip high-NA, transitioning directly to Hyper-NA. However, this is under the premise that Hyper-NA equipment has reached a certain level of reliability.

Intel was the first foundry to adopt high-NA EUV technology. Last year, its foundry business suffered a USD 7 billion loss, and in the first quarter of this year, it faced a record operational loss. One of the reasons for these financial challenges may be contributed to the cost burden of being an early adopter of the next-generation EUV equipment.

ASML has stated that high-NA EUV will enable Intel to produce chips with process nodes from 2 nanometers down to 14 angstroms (1.4 nanometers) and from 10 angstroms (1 nanometer) down to 7 angstroms (0.7 nanometers). ASML also mentioned that Hyper-NA will be essential for future angstrom-scale processes, as it can reduce the risks associated with multi-patterning processes, the report noted.

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• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] EUV as a Strategic Asset in the Most Advanced Processes: Progress in Intel/TSMC/Samsung’s Adoptions

(Photo credit: ASML)

According to a previous report from Nikkei citing sources, TSMC is rumored to be entering the fan-out panel-level packaging sector. As cited in a report from UDN, Intel and Samsung have also announced plans to invest in this area. With TSMC, the leading wafer foundry, joining the fray, the three semiconductor giants are set to compete in fan-out panel-level packaging.

TSMC stated yesterday that the company is closely monitoring the progress and development of advanced packaging technologies, including panel-level packaging technology.

Nikkei reported that in response to future AI demand trends, TSMC is collaborating with equipment and material suppliers to develop new advanced chip packaging technology. This technology uses a rectangular substrate for packaging, replacing the current traditional circular wafer, to accommodate more chipsets on a single wafer. The report further mentioned that TSMC’s research is still in its early stages and might take several years to commercialize, but it represents a significant technological shift.

Reportedly, TSMC previously considered the challenge of using rectangular substrates to be too high, requiring substantial time and effort from both the company and its suppliers, along with upgrades or replacements of many production tools and materials.

Nikkei  also mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

TSMC is expanding its advanced chip packaging capacity, with the expansion of the Taichung plant mainly for NVIDIA, while the Tainan plant is primarily for Amazon and its chip design partner Alchip Technologies.

TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips in two years.

Samsung and Intel have also recognized the aforementioned issues and are investing in next-generation advanced packaging technologies.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

Intel is planning to launch the industry’s first glass substrate solution for next-generation advanced packaging, with mass production scheduled between 2026 and 2030. Intel anticipates that data centers, AI, and graphics processing—markets that require larger volume packaging and higher-speed applications and workloads—will be the first to adopt this technology.

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• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] Samsung Reportedly Targets Q4 Trial Production of SiP Glass Substrate, Competing with Intel in the Advanced Packaging Market

(Photo credit: Intel)

While TSMC faces overwhelming demand for its 3nm technology, with orders from major clients like Apple and NVIDIA pouring in, Intel has now announced its progress on the 3nm technology. According to the latest report by Tom’s Hardware, Intel 3 has entered high-volume production at two sites, the Oregon and Ireland factories, with datacenter-related applications being the node’s primary focus.

However, the capacity seems to be mainly allocated to in-house chips for now. Citing Walid Hafez, Vice President of Foundry Technology Development at Intel, the report notes that Intel’s recently launched Xeon 6 “Sierra Forest” and “Granite Rapids” processors are being manufactured with the company’s 3nm node. Eventually, Intel will utilize this production node to produce datacenter-grade processors for its customers, the report states.

According to Tom’s Hardware, in addition to the standard Intel 3, Intel will also provide various versions for its 3nm node. The semiconductor giant plans to offer Intel 3T, which supports through silicon vias and can serve as a base die. Looking ahead, Intel aims to introduce the feature-enhanced Intel 3-E for chipsets and storage applications, as well as the performance-enhanced Intel 3-PT, designed for various workloads such as AI, HPC, and general-purpose PCs.

According to the report, the Intel 3 process offers both higher performance and increased transistor density, and it supports 1.2V for ultra-high-performance applications. In terms of performance, Intel claims that the new node will deliver an 18% improvement compared to Intel 4.

Regarding major competitors’ development on the 3nm node, TSMC is reported to receive strong demand from clients like Apple and NVIDIA, booking its capacity through 2026, and possibly leading to a price increase by over 5% in the node.

Like Intel, TSMC also offers various choices for its 3nm process. The members of TSMC’s 3nm family include N3, N3E, N3P, as well as N3X and N3A.

As the existing N3 technology continues to be upgraded, N3E, which began mass production in the fourth quarter of last year, targets applications such as AI accelerators, high-end smartphones, and data centers.

N3P is scheduled for mass production in the second half of this year and is expected to become mainstream for applications in mobile devices, consumer products, base stations, and networking through 2026. N3X and N3A are customized for high-performance computing and automotive clients.

On the other hand, Samsung’s second-generation 3nm production line in South Korea will reportedly commence operations in the latter half of this year  The first product to be manufactured on this line will reportedly be the application processor (AP) for the upcoming Galaxy Watch7, tentatively named “Exynos W1000,” which is expected to be unveiled in July.

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• [News] Intel CEO Gelsinger Unveils Lunar Lake Processors, Giving Credit to TSMC
• [News] CoWoS Booming, TSMC Price Hikes Reportedly Imminent

(Photo credit: Intel)

As tech heavyweights eagerly pursue more market share in the AI sector, the battle for talents in the semiconductor industry has also heated up. According to the latest report by The Chosun Daily, citing LinkedIn data as of June 18, NVIDIA has become the hottest tech talent hub, not only drawing talents from semiconductor giants, but recruiting from memory companies in full swing.

According to the report, NVIDIA employs 89 former TSMC employees, while only 12 former NVIDIA employees have joined TSMC. Moreover, comparing with the number of former NVIDIA employees now at Samsung (278), there are 515 NVIDIA employees coming from Samsung Electronics, which indicates a significant talent migration to the GPU giant.

Regarding the talent war between NVIDIA and Intel, the former has attracted as many as 2,848 employees from Intel, whereas only 544 former NVIDIA employees have joined Intel.

NVIDIA also attracts talents with its charisma in AI from other memory giants. The LinkedIn data cited by the report shows that there are 38 NVIDIA employees previously with SK hynix, with none moving in the opposite direction. In addition, NVIDIA has attracted 159 employees from Micron, whereas only 38 former NVIDIA employees have joined Micron.

Interestingly enough, though Samsung lags behind in the competition with TSMC regarding the advanced nodes, it seems to be attractive to talents from the world’s largest foundry. Data show that there are 195 TSMC employees transitioning to Samsung, while only 24 former employees have joined TSMC.

An industry insider cited by the report observed that Korean semiconductor companies are vigorously recruiting for high-performance memory positions, such as those involving HBM. Moreover, a growing number of master’s and doctoral-level semiconductor experts in South Korea are joining the industry, showing a trend where talent moves from academia to local companies and then to international firms.

(Photo credit: NVIDIA)