Rumors have been circulating that Intel has been working with investment bankers on options to navigate the company through difficulties, which may include selling off its Field Programmable Gate Array (FPGA) unit Altera and halt its investment project in Germany, according to the report by Reuters.

Regarding the status quo of the FPGA market, a report by TechNews states that its applications have been concentrated in small-scale sectors such as communications, defense, and chip prototyping, with Xilinx and Altera dominating the field. As a result, rumors have emerged that Intel might sell its entire Altera division to another chip company looking to expand its product portfolio.

Notably, per industry sources cited in the report from TechNews, it’s further suggested that AMD could be a potential buyer, as it would help the US chip giant expand its FPGA product lineup, which would be more effectively ingrated with its current porfolio.

Altera generated USD 342 million in revenue in the first quarter of 2024, a significant decrease of 58% compared to USD 816 million in the same period last year.

On the other hand, AMD’s Embedded Solutions Division, which includes products acquired from Xilinx in 2022, reported a 46% year-over-year decline in sales to USD 846 million for the first quarter, falling short of Wall Street expectations. Both companies’ recent financial reports have been underwhelming.

In addition to AMD, Marvell, a company specialized in network IC design, has also been reported as a potential buyer for Altera.

Previously revealed in a report by Bloomberg on August 29 citing sources, Intel is said to be considering several potential strategies, including spinning off its product design and foundry businesses, canceling some of its regional facility construction plans, or pursuing mergers. These options are expected to be discussed at the board meeting scheduled for September.

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• [News] Intel Reportedly Mulls to Sell FPGA Unit Altera and Freeze USD 32 Billion German Project amid Crisis
• [News] Lip-Bu Tan Resigns from Intel Board Amid Reported Disagreements

(Photo credit: AMD)

Last week, rumors have been circulating that Intel has been working with investment bankers on options to navigate the company through potholes. Latest update: options may include selling off its FPGA unit Altera and putting a halt to its USD 32 billion investment project in Germany, according to the reports by Reuters and Wccftech.

Citing sources familiar with the matter, the reports suggests that Intel CEO Pat Gelsinger and senior executives are expected to present a plan to the board later this month to revitalize the company.

Their proposal, according to the reports, includes divesting non-essential businesses and cutting down capital expenditures, such as selling off Altera and freezing the construction of the fab project in Magdeburg, Germany.

As Intel would be now unable to allocate funds from its once substantial profits to support Altera, a major producer of field-programmable gate arrays (FPGA) it acquired in 2015 for USD 16.7 billion, the sale of the company has reportedly been brought to the table. In 2023, Intel is said to be planning to spin Altera out through an IPO in three years and sell a portion of its stake through the process, but no date has been set.

Reuters indicates that Altera could also be sold entirely to another chip company interested in expanding its business portfolio, and Intel has quietly started exploring the possibility of such a sale.

On the other hand, due to delays of subsidy approvals. Intel has already been said to postpone its construction of Fab 29.1 and 29.2 in Magdeburg, Germany, as the new timeline now pushes the start of construction to May 2025. The proposal to put a halt to the project would also align with the company’s plan to reduce its capital spending by 17 percent to USD 21.5 billion in 2025, Wccftech notes.

Sources familiar with the matter said that Intel’s plan does not currently include splitting up the company or selling its foundry business to buyers like TSMC, Reuters notes.

An Intel spokesperson declined to comment Sunday, Reuters notes.

Intel is currently facing significant challenges. On August 1, the company announced financial results that fell short of Wall Street expectations and revealed plans to cut over 15% of its workforce.

Shortly after, former Intel board member Lip-Bu Tan has stepped down after just two years. Tan served as the CEO and executive chairman of electronic design automation (EDA) software company Cadence Design Systems Inc.

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• [News] Lip-Bu Tan Resigns from Intel Board Amid Reported Disagreements
• [News] Intel Reportedly Considering Foundry Spin-Off or Merger to Mitigate Losses

(Photo credit: Intel)

In a report by Bloomberg on August 29 citing sources, it’s rumored that Intel Corp. is working with investment bankers to navigate what is described as the most challenging period in its 56-year history.

Reportedly, Intel is said to be exploring various options, including spinning off its product design and foundry businesses, and canceling certain construction plans. Notably, Morgan Stanley and Goldman Sachs have been advising Intel, with merger being one of the options on the table.

Multiple options are expected to be presented at the board meeting in September. According to sources cited by Bloomberg, Intel is unlikely to spin off its foundry business unless absolutely necessary. The company is rumored to favor more moderate approaches, such as delaying certain expansion plans.

Per another report from CNBC, during the Deutsche Bank’s Technology Conference on August 29, Intel CEO Pat Gelsinger acknowledged that the past few weeks have been challenging. He then emphasized that the company is prepared to face the market’s criticism and tackle the challenges ahead.

Gelsinger further mentioned that the surge in AI has led to weaker performance in Intel’s server business, a challenge the company is still working to address. However, he remains optimistic about the future, noting that the finish line is already in sight.

He also mentioned that Intel will soon launch “Lunar Lake,” which he described as the most compelling PC product the company has ever developed.

Intel is currently facing significant challenges. On August 1, the company announced financial results that fell short of Wall Street expectations and revealed plans to cut over 15% of its workforce.

Gelsinger noted that the layoffs would impact approximately 15,000 employees. He acknowledged that Intel’s revenue growth has been below expectations and that the company has not yet benefited from trends like AI. Gelsinger highlighted issues with high costs and low profit margins as well, stating that he never anticipated an easy path ahead.

A report from Reuters also revealed that former Intel board member Lip-Bu Tan has stepped down after just two years. Tan, who was previously the CEO and executive chairman of electronic design automation (EDA) software company Cadence Design Systems Inc..

Read more

• [News] Lip-Bu Tan Resigns from Intel Board Amid Reported Disagreements
• [News] Intel’s Earnings Fall Short, Cutting Over 15% of Workforce

(Photo credit: Intel)

As per sources cited in a report from Reuters, it’s revealed that former Intel board member Lip-Bu Tan stepped down after just two years due to disagreements with CEO Pat Gelsinger and other board members.

Two years ago, former Cadence Design Systems CEO Lip-Bu Tan was invited to join Intel’s board of directors to help reverse the company’s operational decline and restore its position as a chipmaker.

In October 2023, his role was expanded to oversee Intel’s manufacturing operations. However, he reportedly stepped down from Intel’s board last week.

The regulatory filings submitted last week have indicated that Tan’s departure from the board was due to a personal decision to reprioritize various commitments, though he remains supportive of Intel and its critical work.

Yet, Reuters further reported that Lip-Bu Tan, a seasoned semiconductor industry veteran, expressed frustration bloated workforce, risk aversion, and lagging AI strategies. This suggests uncertainty around Intel’s efforts to return to profitability.

As of now, neither Intel nor Tan’s venture capital firm, Walden Catalyst, have commented on the matter.

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• [News] The Semiconductor Giant Falling from Grace: Intel and the CEOs Who Changed Its Destiny
• [News] Intel Has Offloaded Stake in ARM, Reportedly Raising nearly USD 150 Million

(Photo credit: Intel)

Earlier in June, Samsung updated its roadmap in the Angstrom era, stating that its 2nm node optimized with backside power delivery network (BSPDN), referred to as SF2Z, will enter mass production in 2027. Now, according to the latest report by the Korea Economic Daily, compared with the traditional front-end power delivery technology, BSPDN is said to reduce the size of Samsung’s 2nm chip by 17%.

Citing Lee Sungjae, vice president of the Foundry PDK Development Team at Samsung, on Thursday, the report also notes that by applying BSPDN to its 2nm chips, Samsung is expected to improve the product’s performance and power efficiency by 8% and 15%, respectively.

Lee’s remarks was the first time a Samsung foundry business executive provided details publicly regarding its BSPDN roadmap. The report explains that by positioning the power rails on the back of the wafer to remove bottlenecks between power and signal lines, the production of smaller chips would be easier.

However, Samsung is not the first semiconductor giant to adopt this technology. Among the Big Three in the foundry sector, Intel is at the forefront, aiming to produce chips with BSPDN technology, which it calls PowerVia, with Intel 20A (2 nm) in 2024. The tech giant also plans to implement PowerVia on Intel’s 20A along with the RibbonFET architecture for the full-surround gate transistor.

According to Intel, power lines typically occupy around 20% of the space on the chip surface, while its self-developed PowerVia’s backside power delivery technology saves this space, allowing more flexibility in the interconnect layers.

On the other hand, foundry leader TSMC reportedly plans to integrate its backside power delivery technology, Super PowerRail architecture, and nanosheet transistors in its A16 chip in 2026.

In addition to BSPDN, Samsung also revealed its roadmap about the next-generation gate-all-around (GAA) technology, which the company was first introduced in 2022, according to the report.

Samsung plans to begin mass production of 3 nm chips based on its second-generation GAA technology (SF3) in 2H24 and will also implement GAA in its upcoming 2 nm process, the report notes.

According to Lee, SF3 has enhanced chip performance by 30%, improved power efficiency by 50%, and reduced chip size by 35% compared to the chips produced with the first-generation GAA process. Coupling with the adoption of BSPDN, the two technologies can further reduce the chip size for Samsung.

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• [News] Samsung Unveils Next-gen 2nm Node Roadmap; SF2Z with Backside Power Delivery to Enter Production in 2027
• [News] TSMC’s Backside Power Delivery Reportedly Set for 2026, Benefiting the Supply Chain

(Photo credit: Samsung)