Per a report from TechNews, during Intel’s earnings call last week, CEO Pat Gelsinger stated that the supply of Core Ultra processors in the second quarter is limited due to insufficient wafer-level assembly capacity.

Gelsinger mentioned in the meeting that with the increasing demand for AI PCs and customers continually adding processor orders to Intel due to Windows update cycles, Intel’s AI PC CPU shipments for 2024 are expected to surpass the originally set target of 40 million units. In response, Intel is actively ramping up production to meet customer demand, with the current supply bottleneck primarily concentrated in the backend wafer-level assembly.

Wafer-level assembly is a technology where packaging is done on wafers before they are cut into chips, widely utilized in processors like Meteor Lake and future Core Ultra processors. However, in the face of overwhelming demand, this production bottleneck has led Intel’s Consumer Computing Division to anticipate second-quarter revenue to be roughly equivalent to that of the first quarter, around USD 7.5 billion.

To address this issue, Intel is actively enhancing its wafer-level assembly capacity to meet the growing orders. It is expected that the current tight situation will be alleviated in the second half of 2024, facilitating further revenue growth for the Consumer Computing Division.

As per previous report by Economic Daily News, Intel has advanced packaging capacity in Oregon and New Mexico in the United States and is actively expanding its advanced packaging capabilities in its new facility in Penang. It is noteworthy that Intel once stated its intention to offer customers the option to only use its advanced packaging solutions, expected to provide customers with greater production flexibility.

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• [News] From Technical Prowess to Integration Capability, TSMC and Intel Target Advanced Packaging to Seize Ecosystem Opportunities
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(Photo credit: Intel)

TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

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• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] Intense Competition with Samsung and Intel in Advanced Processes; TSMC Speeds Up 2nm Progress

Henri Richard, head of Rapidus Design Solutions, the US subsidiary of Japan’s semiconductor foundry startup Rapidus, and former Chief Marketing Officer at processor giant AMD, indicates that Rapidus aims to position itself as a filler of market gaps during the interview with global media The Register.

Rapidus Design Solutions, established by Rapidus in this month, is expected to bolster ties with US semiconductor design companies and wafer manufacturing technology providers like IBM. Henri Richard reportedly notes that the AI boom is boosting the advanced semiconductor foundry market, albeit with understated demand and ongoing capacity constraints. Thus, in this market trend, he asserts that even if these technologies don’t necessarily confer a competitive edge, the limitations in capacity alone should suffice to ensure Rapidus’ success.

Established in August 2022, Rapidus was jointly founded by eight Japanese companies, including Toyota, Sony, NTT, NEC, Softbank, Denso, Kioxia (formerly Toshiba Memory Corporation), and Mitsubishi UFJ, who invested collectively in its establishment. As per Rapidus’ plan, they aim to commence mass production of 2-nanometer process technology in 2027, significantly lagging behind major global players like TSMC, Intel, and Samsung.

TSMC and Samsung previously planned to mass-produce 2nm chips in 2025, while Intel is anticipated to be the first to achieve commercialization of 2nm chips. Industry sources cited by the The Register’s report also view this timing as unfavorable for Rapidus.

However, Henri Richard believes that the semiconductor process technology has reached a turning point. Assessing the success of suppliers solely based on production timelines is narrow-minded; competitiveness stems from various factors beyond production schedules.

Based on these factors, Rapidus positions itself as a fill-in player in the advanced manufacturing market, targeting small AI chip design companies as its primary market. While competitors focus on serving large clients, Rapidus aims to win over these smaller clients by offering comprehensive support services. By serving numerous small chip design companies, Rapidus can better understand the specific needs of AI chip users, rather than insisting on the latest process technology for all chips.

Henri Richard emphasizes that Rapidus itself has limited scale and cannot initially serve too many clients simultaneously. It is expected that Rapidus’s initial client base will not exceed 6 companies, allowing them to accumulate experience and capabilities.

Although there are geopolitical issues currently, establishing facilities in the US is not on Rapidus’s immediate agenda. Meanwhile, Japan represents a relatively favorable geographic location for Rapidus, offering clients a risk-diversification option.

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• [News] Global Acceleration in the Construction of 2nm Wafer Plants
• [News] Rapidus, the First 2nm Client, to Manufacture AI Chips for Tenstorrent

(Photo credit: Rapidus)

U.S. Commerce Secretary Gina Raimondo recently stated that chips used by the Chinese company Huawei in their earlier Mate 60 Pro smartphone are not as advanced as those produced in the United States.

According to a report from Reuters, Huawei has been under trade restrictions since 2019, surprised the global industry and the U.S. government in August 2023 by unveiling a new smartphone featuring advanced chips. Despite Washington’s ongoing efforts to weaken China’s capabilities in advanced semiconductor research and production, the Huawei Mate 60 Pro is still regarded as a symbol of technological breakthrough in China.

Following the release of the chips used in the Mate 60 Pro, many believed that Gina Raimondo’s efforts to restrict Chinese semiconductors were futile. However, Gina Raimondo recently refuted this viewpoint. She pointed out that the new chips introduced by Huawei are not as capable and lag behind U.S. chips by several years in performance, indicating that U.S. export controls on China are effective.

The same report indicates that Washington has been striving for years to weaken China’s capabilities in advanced chip production and the manufacture of equipment required for these chips. The concern is that these chips could be used to enhance China’s military capabilities, with Huawei being a key player.

Therefore, after Huawei was placed on the U.S. government’s Entity List for export control in 2019, related U.S. suppliers struggled to obtain licenses to ship goods to Huawei. Notably, the sources cited in the report cited by Reuters on March 12th once stated that Intel’s competitor, AMD, had applied for a similar license to sell comparable chips in early 2021 but did not receive approval from the US Department of Commerce.

Nevertheless, Intel has been granted licenses worth billions of dollars to continue selling products to Huawei. Additionally, Huawei has also launched its first artificial intelligence notebook featuring Intel chips this month, leading to further controversies. Moreover, as per reports from The Register, Intel is reportedly preparing to follow in NVIDIA’s footsteps by developing “special edition” versions of its AI acceleration chips, Gaudi 3, for the Chinese market.

When asked if the White House’s stance on business with China is tough enough, Gina Raimondo emphasized the need for accountability from companies and everyone alike. She acknowledged that it wasn’t popular with suppliers when she told them they couldn’t sell semiconductor products to China, but ultimately she made that decision.

The emergence of the new generation of Huawei smartphones has also prompted the US administration to conduct dismantling reviews and gain insights into the technology details behind the chips, which are the most advanced semiconductors produced by China to date. However, few details about the related review have been disclosed.

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• [News] Following in NVIDIA’s Footsteps? Intel Reportedly Plans to Launch Chinese Version of AI Chips
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(Photo credit: iStock)

Micron, the largest memory manufacturer in the United States, is expected to receive over USD 6 billion in funding from the Department of Commerce to assist with the costs of local factory projects, as part of efforts to bring semiconductor production back to U.S. soil.

According to a report from Bloomberg, sources revealed that the funding has not been finalized yet and could be announced as soon as next week. It is still unclear whether Micron plans to seek further loans through the “Chip Act” in addition to direct funding.

Micron Technology, the U.S. Department of Commerce, and representatives from the White House all declined to comment on the reported funding.

The U.S. “Chip Act” provides semiconductor companies with USD 39 billion in direct funding and USD 75 billion in loans and loan guarantees to revitalize the U.S. semiconductor manufacturing industry, which has shifted production to Asia over the past few decades. U.S. Commerce Secretary Gina Raimondo stated that approximately USD 28 billion of this funding will be allocated towards advanced manufacturing processes.

So far, the Department of Commerce has announced six grants, with three provided to established semiconductor companies. Specifically, TSMC received USD 6.6 billion USD, Samsung received USD 6.4 billion, and Intel received USD 8.5 billion.

As per the same report from Bloomberg, Micron has committed to building up to four factories in New York and one in Idaho. However, Micron CEO Sanjay Mehrotra emphasized in March that these plans require Micron to obtain sufficient chip subsidies, investment tax credits, and incentives to address the cost differentials compared to expanding overseas.

Raimondo previously stated that the Department of Commerce will prioritize funding projects that commence before 2030. Per to previous documents from Micron cited by Bloomberg, among the four planned factories in New York, only two new factories may meet this requirement, with the other two not expected to start operations until 2041. Insiders suggest that this could mean that Micron’s subsidies may only support the first two factories in New York.

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• [News] The US Administration Rumored to Announce USD 7 Billion Grant for Samsung to Boost Chip Capacity
• [News] TSMC Receives USD 6.6 Billion for Chipmaking from the US Government, Commits to Constructing Third Fab