The semiconductor industry, driven by AI, is entering a new upward cycle. According to a forecast report from SEMI, after the trough in 2023, the total sales of equipment in 2024 will hit a new high, with growth momentum continuing into 2025. Among this trend, per a report from Commercial Times, major companies including TSMC, Intel, Samsung, SK hynix, and Micron are all actively preparing, with plans to continue increasing capital expenditure next year in preparation for the AI era.

TSMC and Intel are the most proactive foundries. Intel plans to increase its capital expenditure by 2% in 2024, reaching USD 26.2 billion; TSMC’s capital expenditure for this year is expected to be between USD 28 billion and USD 32 billion.

The same report further cited sources, indicating that TSMC’s capital expenditure this year will reach the upper end of the estimated range. Next year, the upper limit is expected to increase by another USD 5 billion to USD 37 billion, potentially reaching the second-highest level in its history.

It’s reported that customer demand for TSMC’s 2nm process capacity has exceeded expectations. In addition to Apple securing the first batch of TSMC’s 2nm capacity, non-Apple customers are also actively planning for advanced processes. TSMC continues to advance its goal of mass production of the 2nm process by next year.

Another source cited by Commercial Times reveals that TSMC accelerated equipment orders in the second quarter and further increased momentum in the third quarter, primarily to ensure the smooth launch of the 2nm process by mid-next year.

In the HBM sector, Samsung and SK hynix are reportedly raising funds to prepare for significant production expansion in 2025.  A report from Korean media outlet Korea Economic Daily (KED) indicated that Samsung Electronics and SK hynix are considering applying for loans from the Korea Development Bank, with planned loan amounts of KRW 5 trillion (roughly USD 3.6 billion) and KRW 3 trillion (roughly USD 2.2 billion), respectively.

Micron’s capital expenditure plan for the 2024 fiscal year is about USD 8 billion. In the fourth quarter of the 2024 fiscal year, Micron will spend approximately USD 3 billion on fab construction and new wafer fab equipment (WFE). For the 2025 fiscal year, Micron plans to significantly increase its capital expenditure, targeting 30% of its revenue, or about USD 12 billion. Earlier, Micron’s Chief Operating Officer, Manish Bhatia, stated that the scale of the HBM business is expected to expand to several billion dollars in the 2025 fiscal year.

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• [News] TSMC’s Capital Expenditure to Surge Next Year, Driven by Rising 2nm Demand
• [News] Micron Slightly Raises Capital Expenditure for 2024, HBM Expected to Further Drive Revenue Growth in 2025
  

(Photo credit: Micron)

Recently, Intel, AMD, Samsung, LG Innotek, and SKC’s US subsidiary Absolics have all highly focused on glass substrate technology for advanced packaging. Due to its excellent performance, glass substrate technology has become a rising star in the field of advanced packaging.

In September 2023, Intel announced the so-called “next-generation advanced packaging glass substrate technology,” claiming it could revolutionize the entire chip packaging field. Glass substrate refers to the replacement of organic materials in organic packaging with glass, rather than replacing the entire substrate. Therefore, Intel will not mount chips on pure glass; instead, the core material of the substrate will be made of glass.

Intel stated that glass substrates could lay the foundation for achieving an astounding one trillion transistors on a single package within the next decade. Based on its promising prospect, rumors surface recently that Intel plans to mass-produce glass substrates as early as 2026. Intel has invested approximately a decade in glass substrate technology and currently has a fully integrated glass research line in Arizona, USA. The company stated that the production line costs over USD 1 billion and requires collaboration with equipment and material partners to establish a complete ecosystem. Currently, only a few companies in the industry can afford such an investment, and Intel seems to be the only company so far to successfully develop glass substrate.

Apart from Intel, SKC’s US subsidiary Absolics, AMD, and Samsung also see the broad development prospect of glass substrate.

In 2022, SKC’s US subsidiary Absolics invested around KRW 300 billion to establish the first factory dedicated to producing glass substrate in Covington, Georgia, USA. Recently, the company announced that the factory has been completed and has begun mass production of prototype products. Industry analysts believe this marks a critical moment for the global glass substrate market.

Samsung has formed an alliance composed of Samsung Electro-Mechanics, Samsung Electronics, and Samsung Display to develop glass substrate, aiming to start large-scale mass production in 2026 and commercialize the technology faster than Intel. It’s reported that Samsung Electro-Mechanics plans to install all necessary equipment on a pilot production line by September this year and commence operations in the fourth quarter.

AMD plans to launch glass substrate between 2025 and 2026 and to collaborate with global component companies to maintain its leading position. According to Korean media reports, AMD is conducting performance evaluation tests on glass substrate samples from several major global semiconductor substrate companies, intending to introduce this advanced substrate technology into semiconductor manufacturing.

Currently, with the emergence of new companies like SCHMID and the participation of laser equipment suppliers, display manufacturers, and chemical suppliers, the industry is gradually forming some new supply chains around glass core substrate, and create a diversified ecosystem.

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• [News] Samsung Bullish on Glass Substrate Applications, Setting Up Production Line for Mass Production Starting in 2026

(Photo credit: Intel)

After Samsung announced a major breakthrough in 2nm, securing the first batch of orders from Japanese AI company Preferred Networks, its rival TSMC is also advancing. According to reports from Wccftech and ET News, TSMC is set to begin trial production of 2nm chips next week, which would reportedly be used in the upcoming iPhone 17 lineup in 2025.

The reports note that the trial production will be conducted in TSMC’s Baoshan Plant in Hsinchu, northern Taiwan, as facilities have been brought in during the second quarter. The iPhone 17 lineup is rumored to be the first to feature TSMC’s 2nm chips. Following that, the chips will likely be used in the 14-inch and 16-inch MacBook Pro models.

According to a previous report by MoneyDJ, TSMC’s 2nm production bases are located in Hsinchu Science Park and Kaohsiung, southern Taiwan, while the mass production is expected to kick off in Hsinchu first, with an initial monthly capacity of approximately 30,000 to 35,000 wafers.

Apple and TSMC share a long history of partnership, as the smartphone giant’s A17 Pro, M3 and M4 chips are all manufactured with TSMC’s 3nm node. As TSMC reportedly plans to enter 2nm trial production next week for Apple’s M5 chip, the company’s target for 2nm to enter mass production in 2025 would be on schedule, Wccftech notes.

According to Wccftech, The M5 chip, compared to its predecessor M4, is expected to have performance increase of 10 to 15 percent and a power consumption reduction of up to 30 percent compared to current 3nm-based chips.

Regarding the progress of other semiconductor heavyweights on 2nm, Samsung is said to commence mass production of 2nm chips for mobile devices by 2025. The initial SF2 2nm process will be ready next year, followed by an enhanced version, SF2P, in 2026. Its latest 2nm process, SF2Z, has incorporated optimized backside power delivery network (BSPDN) technology, and will enter mass production in 2027.

On the other hand, Intel’s 20A manufacturing technology (2nm) is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and BSPDN.

Read more

• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] TSMC Reportedly Invests over USD 12.3 Billion in EUV, Advancing in 2nm Production

(Photo credit: Apple)

While NVIDIA is likely to face accusations from the French antitrust regulators, the Non-NVIDIA Alliance like the UALink (Ultra Accelerator Link) Alliance and the UXL Foundation are reportedly launching a counterattack, significantly increasing their efforts in developing specialized ASICs.

According to a report from Commercial Times, relevant semiconductor intellectual property (IP) is expected to be widely adopted. The sources cited by the report point out that Taiwanese manufacturers, benefiting from their leading position in wafer foundry and comprehensive ASIC and IP layout, are poised to capitalize on the rise of the Non-NVIDIA Alliance.

The report further cites sources, indicating that major Taiwanese ASIC manufacturers such as Global Unichip, Faraday Technology, and Progate Group Corporation (PGC), along with silicon IP companies M31 Technology Corporation, eMemory, and the Egis Technology Group, are actively expanding in this field.

In order to challenge NVIDIA’s dominance in the market, UALink (Ultra Accelerator Link) Alliance, led by tech giants such Intel and AMD, was formed in May. The alliance aims to establish a new standard for AI accelerator links, aiming to challenge NVIDIA’s  NVLink.

Furthermore, the UXL Foundation’s Open Source Software Project, supported by tech giants Qualcomm, Google, and Intel, is said to be looking to rival NVIDIA’s CUDA software. By providing alternative software solutions, it aims to diminsh NVIDIA’s dominance in the AI field.

Semiconductor industry sources cited in the same report also note that CSPs are accelerating the development of their own chips, with Taiwanese manufacturers actively entering the market.

Although Broadcom and Marvell currently offer diversified design services, Taiwanese manufacturers have an advantage due to the tightly-knit semiconductor supply chain. This enables complete solutions for both chip manufacturing and packaging within Taiwan, giving them a strategic edge over competitors by being close to both the market and factories, thereby enhancing their position in the ASIC sector.

Global Unichip and PGC leverage TSMC as a strong ally. Reportedly, Global Unichip holds AI-related ASIC orders from Microsoft and is gradually finalizing collaborations with major South Korean companies, with business operations expected to improve in the second half of the year.

On the other hand, Faraday Technology closely collaborates with Intel, developing SoCs using Intel’s A18 process. Meanwhile, industry sources cited by the report suggest that Intel’s Gaudi series AI chips might seek collaboration opportunities beyond just working with Alchip.

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• [News] Novatek, a Major Driver IC Manufacturer, Reportedly Eyes Entry into ASIC and Silicon IP Battlefields

(Photo credit: Shutterstock)

Semiconductor equipment giant ASML plans to launch Hyper-NA Extreme Ultraviolet (EUV) machines by 2030, signaling the advent of the Angstrom era for semiconductor processes below 1 nanometer. However, according to a report from The Chosun Daily, the high cost of this equipment may cause TSMC, Samsung, and Intel to hesitate.

Reportedly, it’s said that ASML introduced a higher numerical aperture (high-NA) EUV machine last year, which outperforms existing EUV technology. Now, ASML is rumored to release the Hyper-NA EUV for sub-1nm processes by 2030. This development brings up significant strategic considerations for TSMC, Samsung, and Intel due to the substantial expense involved in acquiring such advanced equipment.

According to the report, currently, each EUV machine costs approximately USD 181 million. The new generation high-NA EUV machines cost from USD 290 million to USD 362 million per unit, while the expected cost for Hyper-NA EUV could exceed USD 724 million, namely, about twice the price of the previous generation.

The same report further points out that TSMC plans to maximize the capabilities of its existing EUV equipment and utilize them through multi-patterning techniques. Simultaneously, the company is evaluating the scale at which additional equipment may be introduced.

A source cited in the report mentioned that though TSMC adopted EUV technology after Samsung, it has managed to mitigate the investment burden of adopting new equipment by upgrading existing tools and employing multi-patterning techniques effectively.

The same source also indicated that TSMC is particularly interested in multi-patterning techniques. By leveraging its extensive expertise and existing EUV infrastructure, TSMC has developed multi-patterning processes, aiming to delay the adoption of high-NA and Hyper-NA EUV as much as possible.

TSMC has openly expressed concerns about the high cost of the new generation high-NA EUV machines. TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, has indicated that the development of 1.6 nanometer processes may not necessarily require high-NA technology.

Zhang further mentioned that the decision to adopt the new ASML technology would depend on where it offers the most economic benefits and the technical balance they can achieve. He declined to disclose when TSMC might purchase High-NA EUV from ASML. 

As per the same report, Samsung is also considering the adoption of high-NA equipment but is adjusting its long-term roadmap with the emergence of Hyper-NA. According to another source cited by the report, it claimed that choosing high-NA now may not be the best option for long-term plans that involve processes below 1 nanometer.

The source continued that given the emergence of Hyper-NA, one approach might be to maximize the use of existing EUV and skip high-NA, transitioning directly to Hyper-NA. However, this is under the premise that Hyper-NA equipment has reached a certain level of reliability.

Intel was the first foundry to adopt high-NA EUV technology. Last year, its foundry business suffered a USD 7 billion loss, and in the first quarter of this year, it faced a record operational loss. One of the reasons for these financial challenges may be contributed to the cost burden of being an early adopter of the next-generation EUV equipment.

ASML has stated that high-NA EUV will enable Intel to produce chips with process nodes from 2 nanometers down to 14 angstroms (1.4 nanometers) and from 10 angstroms (1 nanometer) down to 7 angstroms (0.7 nanometers). ASML also mentioned that Hyper-NA will be essential for future angstrom-scale processes, as it can reduce the risks associated with multi-patterning processes, the report noted.

Read more

• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] EUV as a Strategic Asset in the Most Advanced Processes: Progress in Intel/TSMC/Samsung’s Adoptions

(Photo credit: ASML)