Intel has reportedly delayed its construction of Fab 29.1 and 29.2 in Magdeburg, Germany, as the new timeline now pushes the start of construction to May 2025, according to a report by tom’s Hardware, citing German media outlet Volksstimme.

However, the fabs could still become operational by late 2027 or early 2028 if the semiconductor giant expedites construction and tool installation, the report stated. The current scenario does seem challenging though, as the company has to deal with black soil removal issues and delays in subsidy approvals.

In June 2023, Intel reached an agreement with Germany, announcing the signing of an amended investment memorandum. The plan involves investing over EUR 30 billion to construct two new fabs in Magdeburg, of which the German federal government has agreed to provide a subsidy of EUR 10 billion, including incentives and subsidies from the European Chips Act and government initiatives.

Originally, construction was scheduled to begin in the first half of 2023 but was postponed to summer 2024 due to delays in subsidy approvals. Until recently, the EU Competition Authority has not yet approved the around EUR 10 billion subsidy.

The topsoil removal process, as required by law, thus, has been rescheduled to May 2025. In the meantime, Intel and the state are adjusting plans, focusing on infrastructure development and land acquisition to prepare for the delayed construction, according to the aforementioned reports.

Fab 29.1 and Fab 29.2 were initially planned to begin operations in late 2027, utilizing Intel’s 14A (1.4nm) and 10A (1nm) process nodes for specific products on Intel’s roadmap, the reports noted. Although Intel has some time to ramp up the fab even if it becomes ready by mid-2028, the schedule remains tight.

The report from Volksstimme even indicated that Intel now estimates it will take four to five years to build the two factories, with production potentially starting in 2029 or 2030.

On the other hand, regarding major semiconductor companies’ overseas expansion progress in Germany, in mid-May, TSMC confirmed that it will start construction of its first chip plant in Europe in Dresden, eastern Germany, in the fourth quarter of this year, with production expected to begin in 2027.

It is understood that TSMC’s fab in Germany will initially focus on the 22-nanometer process, mainly producing automotive microcontrollers. There is a possibility of expanding to produce more advanced chips in the future.

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• [News] Intel Submits Conceptual Drawings for Fab Construction in Germany, Installing High-NA EUV Exposure Machines
• [News] TSMC Confirms Construction for Its First European Chip Plant to Commence in Q4, as Scheduled

(Photo credit: Intel)

This May, we have witnessed two different approaches to the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment between semiconductor giants. Intel has secured the first batch of High-NA EUV kits from ASML, which will allegedly be used on its 18A (1.8nm) and 14A (1.4nm) nodes. On the other hand, TSMC stated that the company will not utilize this new lithography technology in its upcoming A16 (1.6nm) process.

High-NA EUV machines may be critical for companies aiming to produce chips beyond 2nm, but are they must-have?

Looking back in history, the industry used to believe that when the U.S. prevented EUV exports to China, the act would limit China’s progress in 7nm. However, China’s largest foundry, SMIC, is rumored to produce 5-nm chips for Huawei this year, without the need for EUV lithography machines.

When examining TSMC’s trajectory on EUV itself, it is worth mentioning that the company took a more cautious stance, as well. When Samsung began using EUV in its 7nm process in 2018, TSMC successfully launched its first 7nm production line using mature DUV lithography.

It was not until the stability and maturity of EUV had been confirmed that TSMC started to use EUV in its N7+ process, which took place in 2019. In the end, in spite of Samsung’s early adoption of EUV, yield issues allowed TSMC to overtake them.

Similarly, in the race for the 3nm process, unlike Samsung, instead of rushing to adopt GAAFET, TSMC chose the reliable FinFET route.

Will history repeat itself? Now it would be a good timing to examine TSMC’s strategy on High-NA EUV machines.

High-NA EUV technology: A Cure for All?

According to a report by China’s Jiwei, at the recent 2024 North America Technology Symposium hosted by TSMC, the company revealed that its A16 process would not require the next-generation High-NA EUV lithography machines, with mass production expected in 2026.

An expert cited by Jiwei stated that TSMC’s decision might be due to the higher risk associated with High-NA lithography machines.

The report noted that there would be still quite a few challenges to be resolved, such as supporting light sources for photon shot noise and productivity requirements, solutions for the 0.55 NA’s small depth of focus, computational lithography capabilities, mask manufacturing, and computing infrastructure including new materials. Not to mention there is the necessary debugging and development time to ensure stability, which implies considerable time and hidden costs.

On the other hand, TSMC began to adopt EUV in its N7+ process in 2019, implying the world’s largest chipmaker has committed plenty of time and effort to refine the technology.

According to the report by Jiwei, by optimizing the EUV exposure dose and the photoresist used, as well as improving photomask life, increasing yield, and reducing defect rates, TSMC has achieved significant advancements. Today, the number of EUV lithography machines has increased tenfold, while wafer output nowadays is 30 times that of 2019.

Weigh Between Cost and Technology

In addition to potential technology bottlenecks, higher cost may be another problem. Per a report from Bloomberg, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that while he appreciates the capabilities of High-NA EUV, he finds its price tag to be unlikeable.

As per the same report from Bloomberg, ASML’s new High-NA EUV machine is priced at EUR 350 million (roughly USD 380 million). Jiwei further stated the unit price may more than double, comparing with the current EUV machines (roughly EUR 170 million).

Market demand would be another major concern. Citing an industry insider, Jiwei analyzed that the cost of manufacturing chips with High-NA lithography machines increases significantly. While more chips can be cut from each wafer, more chips need to be sold to recoup the investment.

The report stated that the smartphone AP chip market alone cannot absorb these cost without the supporting demand of AI chips. However, as China, the largest market for AI, is now being restricted by export control measures from the U.S., the overall market demand remain uncertain.

Adoption Timing for High-NA EUV? TSMC May Not Be in a Hurry

Then what would be the right timing for TSMC to adopt High-NA EUV?

The report by Jimwei took the trajectory of EUV as an example. When the industry generally regarded EUV essential in the 7nm node, TSMC successfully launched its first 7nm production line using mature DUV lithography. This strategy allowed TSMC to avoid the imperfections and high costs of EUV lithography at that time.

TSMC waited until 2019 to start the usage of EUV in its N7+ process when the technology has become mature enough. In the end, in spite of Samsung’s early adoption of EUV, yield issues allowed TSMC to win the favor of clients.

Similarly, in the race for the 3nm process, instead of rushing to adopt GAAFET, TSMC chose the reliable FinFET route. Despite Samsung’s early lead with 3nm, their low yields and repeated delays enabled TSMC to surpass them.

TSMC’s previously announced roadmap indicates that the 1.4nm A14 process is expected to be introduced between 2027 and 2028, while the development of the 1nm A10 process is projected to be completed before 2030. The report by Jiwei suggested that TSMC might consider using the next-generation lithography machine only after the 1nm process is in place, potentially adopting the High-NA EUV system around 2029 to 2030.

Read more

• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Nodes
• [News] Intel to Adopt New High-NA EUV, High Costs Could Lead to Increased Losses

(Photo credit: ASML)

On May 20th, Intel announced that the release date for its next-generation processor, Lunar Lake, has been moved up, with official shipments expected in the third quarter. The NPU performance is set to reach 45 TOPS. However, per a report from Economic Daily News, the industry is puzzled by the fact that this chip is bundled with 16GB and 32GB memory, with Intel holding the specification control tightly. Reportedly, this move has disrupted the industry order, and PC manufacturers are said to be privately expressing their dissatisfaction.

It is expected that 20 brands will release 80 models featuring this processor. Combined shipments of Metro Lake and Lunar Lake this year are projected to reach 40 million units. Unlike the previous generation, Lunar Lake’s packaging design integrates LPDDR5x memory into a single package, emphasizing low power consumption.

On May 20th, Microsoft launched its next-generation AI PCs, equipped with a more powerful AI assistant, Copilot, and new features. It also established a new standard for AI PC architecture, “Copilot+ PC.” The initial products all feature Qualcomm’s “Snapdragon X Elite” processors designed with Arm architecture.

Qualcomm’s CPUs in the new PCs are equipped with a Neural Processing Engine (NPE) designed specifically for AI applications, boasting 45 TOPS. This, as per another report from the Economic Daily News, results in a 58% increase in speed and extended battery life compared to Apple’s latest top-tier MacBook, which uses the M3 chip. Additionally, they support Microsoft’s AI chatbot, Copilot.

Intel, on the other hand, made a rare announcement, revealing that its next-generation Lunar Lake will have a total performance exceeding 100 TOPS, with the NPU alone exceeding 45 TOPS—nearly three times that of the previous generation. Additionally, the CPU and GPU combined computing power will exceed 60 TOPS, making it the second qualified processor for Microsoft’s Copilot+ PC platform.

However, it is important to note that according to Intel’s plans, the new generation processors Ultra 5/7/9 will be bundled with memory and shipped together with the CPU. Specifically, the high-end Ultra 9 will be bundled with 32GB of memory, while the Ultra 5 and Ultra 7 will have 16GB and 32GB versions. Per Microsoft’s recommendations, AI PCs need at least 16GB of memory. While Intel’s approach meets this requirement, it limits the ability of brands to adjust specifications and leaves memory manufacturers out of the loop.

In simpler terms, there is still a demand for 8GB memory in lower-end notebooks, and high-end laptops can require more than 64GB of memory. However, Intel’s Lunar Lake constraints make it difficult to plan both high-end and entry-level versions. Industry sources cited in the same report from Economic Daily News indicate that Intel’s next-generation Arrow Lake will not be bundled with memory.

Reportedly, industry sources also state that procurement contracts with memory suppliers have traditionally been long-term, accounting for annual memory requirements. Now, Intel’s bundling of memory with its single platform changes the industry’s ecosystem. Previously, PC brands would develop various combinations (CPU + memory + SSD capacity) for their product lines. However, with Intel defining five laptop CPU + memory specifications, it limits the customization capabilities of PC brands.

With Intel launching Lunar Lake early, AMD is set to counter with its next-generation AI processor Ryzen series named Strix Point in the fourth quarter. The Strix Point processor will feature AI processing power exceeding 50 TOPS, and there will also be an APU, Strix Halo, expected to launch around the end of the year with performance exceeding 60 TOPS, making it a significant player in AI computing power.

CEO Pat Gelsinger recently demonstrated the performance of the Lunar Lake processor, emphasizing that its total AI workload exceeds 100 TOPS, with the NPU contributing 45 TOPS. The CPU features Lion Cove architecture P-cores and Skymont architecture E-cores, while the GPU and CPU together provide over 60 TOPS of computing power. This means Intel’s chip AI performance will be more than three times that of current products, with a total combined performance exceeding 100 TOPS.

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• [News] Battle in AI PCs: Exploring Intel, AMD, and Qualcomm Chips’ AI Computing Power
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(Photo credit: Intel)

Intel’s early adoption of ASML’s High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV) equipment is seen by many as a crucial move for Intel to reclaim its technological leadership. Yet, according to a report from CNA, industry sources cited in the report have warned that the high cost of High-NA EUV could lead Intel to face the dilemma of expanding losses.

As Intel secures High-NA EUV equipment, the Korean media outlet TheElec reported that ASML plans to manufacture five High-NA EUV equipment this year, all of which have been booked by Intel. TSMC’s decision to continue using existing EUV equipment for its A16 process, rather than adopting High-NA EUV, has drawn significant attention and sparked lively discussion.

Per a report from Reuters, Intel CEO Pat Gelsinger has acknowledged that the previous decision to oppose using ASML’s EUV equipment was a mistake, which hampered the profitability of Intel’s foundry business. He stated that, with the adoption of EUV equipment, Intel is now highly competitive in terms of price and performance. There is widespread interest in whether Intel’s early adoption of High-NA EUV equipment will help it regain its position as a technology leader.

On the other hand, TSMC plans to mass-produce its A16 technology by 2026, combining nanosheet transistors with a supertrack architecture, garnering attention from the industry.

Ray Yang, the consulting director at Industry, Science and Technology International Strategy Center of ITRI (Industrial Technology Research Institute), stated that TSMC’s decision not to adopt High-NA EUV equipment for the A16 process was likely made after a comprehensive evaluation.

Yang mentioned that TSMC is undoubtedly aware of the benefits that High-NA EUV equipment can bring. However, given the high costs, TSMC has chosen to meet its customers’ diverse needs through other means.

According to ASML, High-NA EUV equipment increases the numerical aperture from 0.33 to 0.55, providing higher-resolution imaging capabilities. This improvement enhances precision and clarity, simplifies the manufacturing process, reduces production time, and boosts production efficiency.

During a technical symposium in Amsterdam on May 14th, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that ‘I like the high-NA EUV’s capability, but I don’t like the sticker price.’

Each EUV system from ASML costs around USD 180 million, while High-NA EUV equipment is priced at USD 380 million, more than double the cost of EUV.

Ray Yang noted that the importance of advanced semiconductor packaging is increasing and will play a crucial supporting role. He argued that Intel’s rush to acquire High-NA EUV equipment is a case of choosing the wrong battlefield and weapon because High-NA EUV equipment is not the sole decisive factor for future success.

Ray Yang stated that as the global leader in semiconductor foundry services, TSMC has numerous customers, a comprehensive ecosystem, and ample capital. If customers demand and are willing to pay higher prices, TSMC will undoubtedly adopt High-NA EUV equipment.

Yang noted that TSMC is taking a cautious approach to adopting High-NA EUV equipment, likely after thoroughly considering its necessity. If Intel makes significant purchases of High-NA EUV equipment, its future capacity utilization will be worth observing, as it might face the risk of increased losses.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

Read more

• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: ASML)

According to a report from global media outlet Wccftech, China’s largest foundry, SMIC, is rumored to produce 5-nanometer chips for Huawei this year, without the need for extreme ultraviolet (EUV) lithography machines manufactured by Dutch company ASML.

As per a report by Businesskorea, SMIC seems to be able to use old deep ultraviolet (DUV) lithography machines purchased before the sanctions were implemented to manufacture 5-nanometer chips. However, this would incur higher costs and could also affect yields.

Previously reported by the Financial Times, industry sources have indicated that SMIC’s prices for 5-nanometer and 7-nanometer processes are 40% to 50% higher than TSMC’s, and the yield less than one-third of TSMC’s. Later, it was estimated that SMIC’s 5nm chip prices would be up to 50 percent more expensive than TSMC’s on the same lithography, meaning that Huawei would face a tough time selling its Mate 70 series to consumers with a decent margin if it attempts to absorb a majority of those component costs.

Huawei was previously said to be working closely with its local foundry partner to introduce a new Kirin SoC that will be found in the upcoming Mate 70 series, scheduled to be released in October, with SMIC’s 5nm process has been said completed and is ready to mass produce the first batch of wafer.

This means that if Huawei attempts to absorb most of these costs, it will face the challenge of insufficient profit margins when selling the Mate 70 series to consumers. The tech giant may attract customers by promoting its in-house HarmonyOS Next, which is reportedly set to debut with the Mate 70 series. The model is said to be equipped with better efficiency in memory management compared to Google’s Android platform, according to Wccftech.

Meanwhile, Intel has recently secured its supply of the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment from ASML, which the semiconductor heavyweight will allegedly use on its 18A (1.8nm) and 14A (1.4nm) nodes, according to a report from TheElec.

On the other hand, according to sources cited by a report from Economic Daily News, TSMC’s A16 advanced process node might not necessarily require ASML’s latest advanced chip manufacturing equipment, the High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV), due to its expensive price.

Read more

• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Node
• [News] Intel Secures First Batch of High-NA EUV Equipment from ASML, Ahead of Samsung and SK Hynix

(Photo credit: SMIC)