The US-China tech war continues to escalate, as reported by the Financial Times (FT). Beijing has reportedly instructed official institutions in China to refrain from using PCs and servers equipped with microprocessors from Intel and AMD, as well as to reduce procurement of Microsoft Windows operating systems and database software outside of China.

In response to these reports, both Microsoft and Intel have declined to comment, while AMD, China’s Ministry of Finance, Ministry of Industry and Information Technology, and the China Information Security Evaluation Center have not responded to requests for comment from FT reporters.

FT further reveals that Chinese authorities have requested state-owned enterprises to promote localization internally. Intel and AMD are the two major semiconductor giants in the United States, dominating nearly all global market shares of PC processors.

As both Intel and AMD are significant customers of TSMC’s advanced process nodes, this move is expected to influence TSMC’s future order status. Regarding China’s full-scale development of proprietary computer processors, its potential impact on ASIC-related companies in Taiwan remains to be seen.

As per Industry sources cited by the report, they have suggested that this move by Chinese authorities demonstrates their determination to strengthen local semiconductor autonomy and enhance manufacturing and design capabilities. On the manufacturing side, the focus remains on supporting SMIC, while chip design is primarily led by companies such as Huawei and Phytium.

Per the same report, following the release of new guidelines by China’s Ministry of Finance and Ministry of Industry and Information Technology on December 26th last year, officials have begun adhering to the latest standards for PC, laptop, and server procurement this year. They have mandated that government departments at the township level and above, as well as party organizations, must incorporate standards for purchasing “secure and trustworthy” processors and operating systems.

The China Information Technology Security Evaluation Center has published the first list of “safe and reliable” processors and operating systems, all of which are from Chinese enterprises.

Among the 18 approved processors are chips from Huawei and Phytium. Chinese processor manufacturers are utilizing a hybrid architecture combining Intel x86, Arm, and self-developed designs for chip production, while operating systems are sourced from open-source Linux software.

Prior to the speculated tightening of restrictions by China on the United States, a report from Bloomberg citing sources had already signaled that the US government is considering adding Chinese semiconductor companies linked to Huawei to a blacklist.

Currently, companies that have been listed on the entity list by the US Department of Commerce include Huawei, SMIC (Semiconductor Manufacturing International Corporation), and Shanghai Micro Electronics. Additionally, China’s other major memory manufacturer, Yangtze Memory Technology Corp, was added to this restriction list in 2022.

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• [News] US Government Considers Adding ChangXin Memory Technologies to Entity List, Imposing Further Sanctions on Chinese Firms
• [News] US Considers Sanctioning Huawei-Linked Chinese Chip Network, Huawei-Related Enterprises Blacklisted

(Photo credit: iStock)

As TSMC and Intel slow down their plans for building fabs in the United States, the supply chain, according to a report from Nikkei Asia, is also said to delay in following suit, with semiconductor material suppliers like Topco Scientific, LCY Chemical, and Chang Chun Group among those named.

Per the same report citing statements from several industry sources, the construction of these fabs has been either postponed or significantly scaled back due to soaring costs of construction materials and labor, as well as a shortage of construction workers.

While some delays may be temporary, other fab construction projects are being thoroughly reassessed, with no specific timetable for resuming. Suppliers attribute the delays in fab construction plans to the slower-than-expected progress of Intel and TSMC in setting up their facilities.

The sources cited in the report also revealed that Solvay, a leading supplier of high-purity hydrogen peroxide for semiconductor use based in Belgium, has postponed the construction of its Arizona plant due to cost concerns and fears that Intel and TSMC’s expansion progress may take longer than expected.

Meanwhile, another major manufacturer of high-purity hydrogen peroxide for semiconductors, Taiwan’s Chang Chun Group, has significantly scaled back the construction of its new Arizona plant due to costs that have exceeded expectations by several times.

Regarding this issue, Chang Chun Group reportedly opted not to provide comments, while Solvay mentioned they are currently investigating the matter.

Topco Scientific has reportedly pointed out that it has acquired land in Arizona, USA. However, the company is currently adjusting its investment schedule for warehouse logistics in Arizona. This adjustment aligns with the progress and demand of its customers in setting up factories, as well as the local infrastructure planning, which includes water and power supply and road construction.

Per the report citing sources, TSMC originally planned to begin mass production at its Arizona plant in 2024. However, this timeline has now been postponed to 2025. Initial expectations for the second fab’s schedule were set for 2026, but it is now likely to be pushed back to 2027-2028

As per a previous report from TechNews, despite the United States outperforms Taiwan in various aspects for foundry construction, the primary obstacle is regulatory issues.

Due to the unique federal structure of the United States, foundry construction must comply with federal, state, and local regulations, resulting in an exceptionally complex regulatory process. Additionally, environmental policies pose obstacles to foundry construction, particularly due to stringent requirements for environmental protection

The report suggests that to enhance the United States’ competitiveness in the global semiconductor industry, the government needs to streamline regulatory processes, eliminate redundant regulations, and establish expedited pathways to accelerate semiconductor industry construction projects.

Additionally, there should be an acceleration of environmental review processes and investment in the development of alternative materials to ensure sustainable semiconductor material supplies.

With the continued growth in global semiconductor demand, the construction speed and efficiency of US semiconductor fabs will directly impact its position in the global market.

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• [News] TSMC’s 4nm Process Powers NVIDIA’s Blackwell Architecture GPU, AI Performance Surpasses Previous Generations by Multiples
• [News] Opening of TSMC Kumamoto Plant Nears, Yet Delay in Arizona Plant – Why is US Semiconductor Fab Construction Lagging Globally?

(Photo credit: TSMC)

Driven by the AI chip wave, “advanced packaging” emerges as the hottest technology in the semiconductor industry. Its significance extends beyond computational power demands, as the escalating cost of semiconductor processes and the limits of Moore’s Law make the “integration capability” of advanced packaging a crucial weapon for industry players to break through.

According to a report from TechNews, TSMC, Intel, and Samsung have all been deeply involved in advanced packaging for many years and have already introduced corresponding solutions. However, these semiconductor giants are not only focused on this aspect.

In addition to their own technologies, they are actively fostering supply chains, setting standards, and building ecosystems. By accelerating the development of advanced packaging technology, they are also laying the groundwork for their future influence.

Intel, for instance, has chosen to start with standardization by proposing the Universal Chiplet Interconnect Express (UCIe) alliance. Through open specifications and standardized connections, the protocol directly adopts mature standards like PCI Express (PCIe) and the recently developed Compute Express Link (CXL).

The reason for starting with chiplet technology is that in recent years, more and more semiconductor companies have discovered that designing chips using Chiplet architecture and integrating them through advanced packaging technology is more cost-effective than traditional System-on-Chip (SoC) approaches.

Therefore, Intel’s focus on connecting chiplets through standards like UCIe is aimed at providing a standardized interface stack for complete chiplet integration. UCIe supports 2D, 2.5D, and bridge packaging, with future development expected to include support for 3D packaging as well.

Intel’s Packaging Test Technology Development Department’s Senior Chief Engineer, Zhiguo Qian, directly involved in the UCIe Alliance, emphasizes that advanced packaging has become a crucial aspect of semiconductor development, particularly in ensuring the continuation of Moore’s Law.

Qian further points out that when considering the impact of the UCIe standard on the advanced packaging industry, it indeed establishes a standard for interconnecting chiplets within SoCs. This was the original intent behind Intel’s promotion of the UCIe standard alliance.

Currently, advanced packaging is mostly divided into different structures like 2.5D and 3D, and some even classify it as 2.1D or 2.2D, showcasing diverse structural designs across the industry.

However, within these structures, each company has its own proprietary interface solutions, and some even offer multiple solutions. Therefore, to meet customer demands, these standard interconnections must not only be at the forefront of technology but also be compatible with various standards that are open and do not incur any licensing fees.

On the other hand, the UCIe alliance has established various standards, such as the required packaging architectures and interface wiring designs, to achieve the desired performance levels. These standards provide guidelines for customers seeking advanced packaging solutions. By adhering to UCIe standards, customers can anticipate the performance of their chips, without the need for trial and error(in the IC designing stage).

Source: Intel

Currently, companies participating in the UCIe alliance include Qualcomm, AMD, Arm, NVIDIA, TSMC, ASE Group, Winbond Electronics, and Applied Materials, among others, along with semiconductor giants like Samsung. Additionally, Google Cloud, Microsoft, and Meta are members, alongside over 120 other companies.

• TSMC Propels 3D Fabric Alliance

TSMC is also focused on ecosystem development, as evidenced by its announcement of the 3DFabric Alliance within the Open Innovation Platform (OIP) during the 2022 Open Innovation Platform Ecosystem Forum.

In fact, the 3DFabric Alliance is built upon TSMC’s 3DFabric technology introduced in 2020. This technology encompasses a comprehensive solution ranging from advanced processes to silicon stacking and advanced packaging technologies such as CoWoS and InFO.

With an established customer base for its 3DFabric technology, TSMC expanded it into an alliance in 2022. The goal is to assist customers in achieving rapid implementation of chip and system-level innovations while strengthening TSMC’s influence in advanced packaging.

The 3DFabric Alliance marks TSMC’s sixth open innovation platform alliance and is the semiconductor industry’s first alliance aimed at accelerating innovation and enhancing the 3D Integrated Circuit (3D IC) ecosystem in collaboration with partners.

This alliance includes companies in electronic design automation (EDA), silicon intellectual property (IP), design center alliances (DCA)/value chain alliances (VCA), memory, outsourced packaging testing (OSAT), and substrate and testing. Members include Ansys, Cadence, Siemens, ARM, Micron, Samsung, SK Hynix, Amkor, ASE, Advantest, and more.

Source: TSMC

In addition to establishing the alliance, TSMC also introduced the 3Dblox standard during the alliance’s inception. This standard integrates the design ecosystem with validated EDA tools and processes to support 3DFabric technology.

The purpose of this standard is to break the complexity of 3D IC design caused by each EDA supplier using its preferred language. Through the modular 3Dblox standard, key physical stacking and logic connection information in 3D IC design are standardized in a single format, simplifying input and significantly enhancing interoperability among different tools in 3D IC design.

From Intel’s UCIe standard to TSMC’s 3DFabric alliance and 3Dblox standard, it’s evident that in the era of advanced packaging, the key to solidifying the positions and market shares of semiconductor giants lies not only in their individual technological breakthroughs but also in their ability to coordinate and integrate the upstream and downstream industries.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: TSMC)

In 2022, Intel engaged in negotiations with the Italian government, planning to invest USD 5 billion in constructing a packaging and testing facility. This project would also receive subsidies from the Italian government, expected to cover 40% of the construction costs, along with additional subsidies or incentives. Furthermore, Intel intended to establish a research and design center in France, expected to create a complete semiconductor supply chain in Europe.

However, according to a report from Reuters, Italian Minister of Industry Adolfo Urso has indicated that Intel may delay or abandon its investment plans in Italy and France to fulfill its prior commitments in Germany. Nonetheless, Italy has not completely given up on attracting Intel; Adolfo Urso emphasizes that Italy remains very welcoming if Intel changes its mind.

On the other hand, according to another previous report from Reuters, the US government is expected to announce a significant grant for Intel’s Arizona project soon. This grant will be part of the USD 39 billion direct appropriations and USD 75 billion loans and guarantees under the “Chip Act.”

Among the recipients of subsidies under the “Chip Act,” Intel is expected to receive the largest subsidy to date. According to a previous report from Tom’s Hardware, Intel is anticipated to receive a government subsidy of USD 10 billion, with TSMC and Samsung potentially included in the latest subsidy list as well.

Samsung Electronics is, according to its own expectation, investing USD 17 billion to construct a foundry in Taylor, Texas, while TSMC is investing roughly USD 40 billion to build a foundry in Phoenix, Arizona. However, there are rumors suggesting that due to the U.S. prioritizing domestic companies, the expected subsidy amounts for Intel may differ from those for TSMC and Samsung.

The U.S. government enacted the “Chip Act” in 2022, but subsidies have been modest, with only three American companies currently benefiting, including BAE Systems, GlobalFoundries, and Microchip Technology.

In order to accelerate the development of the IDM 2.0 initiative, Intel made a significant expansion decision in 2021, investing approximately USD 20 billion in the Octillo campus in Arizona, USA. This investment involved the construction of two new fabs and the implementation of EUV production lines to support Intel’s 20A and Intel’s 18A process technologies. The new Fab 52 and Fab 62 are expected to commence operations in 2024.

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• [News] Intel Submits Conceptual Drawings for Fab Construction in Germany, Installing High-NA EUV Exposure Machines
• [News] GlobalFoundries Reportedly Becomes Third Recipient of CHIPS Act Subsidy, Receives USD 1.5 Billion

(Photo credit: Intel)

According to sources cited by Reuters,  TSMC is reportedly considering plans to establish a production line for its CoWoS technology in Japan. However, TSMC has yet to make any further decisions, and they have declined to comment on the matter.

CoWoS is an advanced packaging technology that stacks chips to enhance computing power, reduce energy consumption, and save space. Currently, TSMC’s CoWoS production capacity is entirely located in Taiwan.

With the booming development of artificial intelligence, global demand for advanced semiconductor packaging has surged, prompting chip suppliers like TSMC, Samsung, and Intel to strengthen their advanced packaging capabilities.

Previously, TSMC’s CEO, C.C. Wei, stated that the company plans to double its CoWoS output by the end of 2024 and further increase it in 2025. With TSMC recently completing the first phase of construction for its Kumamoto fab in Japan and announcing plans for the second phase, which will involve collaboration with Japanese companies SONY Semiconductor Solutions and Toyota Motor Corporation, with a total investment exceeding USD 20 billion and utilizing 6/7-nanometer advanced processes.

However, Joanne Chiao, an analyst at market research firm TrendForce, suggests that if TSMC establishes advanced packaging capacity in Japan, it may face limitations in scale. It remains unclear how much demand there is in Japan for CoWoS packaging, but most of TSMC’s CoWoS customers are currently in the United States.

Additionally, sources cited by Reuters’ report indicate that TSMC’s competitor, Intel, is also considering establishing an advanced packaging research facility in Japan to deepen ties with local chip supply chain companies.

Meanwhile, Samsung, another competitor of TSMC, is setting up advanced packaging research facilities in Yokohama, Japan, with government support. Furthermore, Samsung is in discussions with Japanese and other companies regarding material procurement, preparing to launch its packaging technology similar to that used by SK Hynix.

Regarding the development of the semiconductor industry in Japan, as mentioned in a previous report from TrendForce, Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development. Japan is strategically positioning itself to reclaim its former glory in the world of semiconductors.

Read more

• [News] Subsidies to TSMC from Japan and China Increase Over Fivefold Annually
• [News] High Efficiency in TSMC Kumamoto Plant Construction Sets Stage for Potential Advanced Packaging Investment in Japan

(Photo credit: TSMC)