Samsung, as per a report from the global media outlet wccftech, has decided to enter the next generation of packaging technology by commencing R&D works for the adoption of “Glass Substrate” by 2026.

The report further indicates that Samsung’s preparation to enter the glass substrate industry for advanced packaging is not actually a new endeavor. As several years ago, competitor Intel had already made strides in this area. The commencement of significant production is expected to begin around 2030. In preparation for large-scale production, Intel has already begun establishing production lines in Arizona, investing USD 1 billion.

To address the current market’s capacity gap, Samsung has also initiated plans to commence glass substrate production.

Currently, under the Samsung Group umbrella, Samsung Electronics is in the process of implementing construction plans for production lines and is also conducting research and development on the application of glass substrates in the field of AI chips.

Additionally, Samsung Group is coordinating various departments within its conglomerate, such as Samsung Display, to further ensure the smooth completion of research and development as well as production efforts related to glass substrates.

The report indicates that through the application of advanced packaging technology using glass substrates, there are several advantages over traditional organic substrate packaging techniques, and it can overcome more technical bottlenecks.

For instance, glass substrates can offer higher strength, ensuring greater durability and reliability, as well as higher interconnectivity. Moreover, glass substrates are thinner than typical organic substrates, enabling the linking of more small chips in advanced packaging technology.

Previously, Intel also elaborated on the glass-based substrate packaging technology. According to Intel’s previous press release, glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

However, despite the many application advantages of glass substrates in the current market, the R&D efforts of various companies have encountered difficulties, impacting the market’s application status.

Currently, Samsung Electronics expects to mass-produce glass substrate products in 2026. Whether it can replace traditional organic substrates and advance packaging technology development will be a focal point of market attention.

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• [News] Glass Substrates in Advanced Packaging With Intel Leads, TSMC Quietly Innovates

(Photo credit: Intel)

Intel has reportedly retained the export licenses that would have prohibited them from selling laptop processor (CPU) chips to the Chinese telecommunications giant Huawei. This signifies that Intel has temporarily preserved its business of providing chips worth hundreds of millions of dollars to Huawei.

According to sources cited by Reuters on March 12th, the US placed Huawei on a trade blacklist in 2019, alleging violations of US sanctions. However, at the end of 2020, the US Department of Commerce granted special licenses to some US suppliers, including Intel, allowing them to sell certain technology products to Huawei.

Still, some sources cited in the report believe that Intel’s license is expected to expire later this year and is unlikely to be renewed.

The sources cited in the same report also stated that Intel’s competitor, AMD, had applied for a similar license to sell comparable chips in early 2021 but did not receive approval from the US Department of Commerce. AMD subsequently protested, claiming that the US government’s differential treatment was unfair.

Regarding this matter, Intel, Huawei, the Commerce Department and the White House declined to comment. AMD did not respond to a request for comment.

As per TrendForce, Intel is forecasted to hold a market share of 68.8% in the CPU market in 2024, while AMD is expected to have a share of 20.2%.

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• [News] China’s Third Big Fund Reportedly Set to Inject USD 27 Billion to Counter US Chip Restrictions
• [News] Huawei Shifts Focus, Prioritizing Production of AI Chips over Mate 60 Series

(Photo credit: iStock)

Recently, IC design company Marvell announced an expansion of its long-term partnership with TSMC to include 2-nanometer technology. They will collaborate on developing the industry’s first 2-nanometer semiconductor production platform optimized for accelerating infrastructure.

Currently, the most advanced production technology in the industry is the 3-nanometer process, manufactured by Samsung Electronics and TSMC. With Intel securing the first ASML lithography machine and updating its latest manufacturing roadmap, and with the increasing collaboration between Rapidus and IBM, the competition for the 2-nanometer advanced process has significantly expanded to include TSMC, Intel, Samsung and  Rapidus.

• Marvell

According to Marvell’s press release, it has stated that Marvell has transitioned from a follower to a leader in integrating advanced node technology into silicon infrastructure.

Marvell first bringing advanced node technology to infrastructure silicon with its 5nm platform, followed by the release of several 5-nanometer designs and the profolio of the first silicon infrastructure product lineup based on TSMC’s 3-nanometer process.

“Tomorrow’s artificial intelligence workloads will require significant and substantial gains in performance, power, area, and transistor density. The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure capable of delivering on the promise of AI,” said Sandeep Bharathi, chief development officer at Marvell.

• TSMC

TSMC commenced mass production of its 3-nanometer process in 2022, with profitability realized starting from the third quarter of 2023. By the fourth quarter of 2023, the 3-nanometer process contributed to 15% of wafer revenue, and its revenue share has been steadily increasing.

According to TrendForce, the foundry market is expected to grow by 7% in 2024, largely attributed to TSMC’s ramp-up of its 3-nanometer process. This has further increased TSMC’s market share.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures. It is anticipated that N2 will commence mass production in 2025, leading the industry in terms of density and energy efficiency.

The N2 backside power delivery solution is slated for release in the latter half of 2025 and is expected to enter mass production in 2026, primarily targeting the High-Performance Computing (HPC) sector.

Furthermore, due to the current high demand for 2-nanometer processes from all AI innovators worldwide surpassing that for 3-nanometer processes, almost all AI innovators are collaborating with TSMC on 2-nanometer process technology. The main applications are primarily focused on high-performance computing (HPC) and smartphones.

Consequently, TSMC has announced plans to expand its production capacity for 2-nanometer processes. Originally, two 2-nanometer fabs were planned for the Kaohsiung facility, but now consideration is being given to constructing a third 2-nanometer fab.

• Samsung

Samsung commenced mass production of its 3-nanometer process in June 2022. According to the latest industry reports, Samsung has developed a “second-generation 3-nanometer” process, renamed as “2-nanometer”, with plans for mass production before the end of this year.

At the 2023 Samsung Foundry Forum, Samsung Electronics unveiled the latest roadmap for its 2-nanometer process. Samsung Electronics President and Head of Foundry Business, Siyoung Choi, disclosed that Samsung will first mass-produce 2-nanometer chips for mobile terminals starting from 2025. Subsequently, in 2026, the technology will be applied to high-performance computing (HPC) products, followed by expansion to automotive chips by 2027.

Unlike TSMC, which opted for Gate-All-Around (GAA) structure at the outset of its 2-nanometer process, Samsung has been utilizing GAA structure since its 3-nanometer process. This suggests that Samsung may have more experience in new structures compared to TSMC, thus giving Samsung an advantage in its 2-nanometer node.

In the past, when Samsung Electronics transitioned from 7-nanometer to 5-nanometer process technology in 2020, the second generation 7-nanometer process technology was renamed as 5-nanometer process technology.

Samsung Electronics’ 7-nanometer process technology became the world’s first to use Extreme Ultraviolet (EUV) lithography in 2019, making it more stable and enabling the company to further shrink transistor sizes. This was also the reason for renaming the second generation 7-nanometer process to 5-nanometer process at that time.

A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.

It is reported that PFN has been collaborating with TSMC since 2016, but this year, it has decided to produce the next generation of AI chips at Samsung’s 2-nanometer node. According to the agreement, Samsung will utilize its latest 2-nanometer chip fab technology to manufacture AI accelerators and other AI chips for PFN.

• Intel

As per Intel’s previously announced plans, the company aims to catch up with and surpass TSMC by 2024 or 2025. At this year’s “Direct Connect” conference hosted by Intel Foundry Services, the company unveiled its latest technological roadmap.

Intel has reported that its primary product, Clearwater Forest, which is under the 18A process, has been completed and is set for production in 2025. Intel’s 18A process is often compared with TSMC’s N2 (2-nanometer) and N3P (3-nanometer) processes in terms of performance, with each company advocating for its own advantages.

Intel CEO Pat Gelsinger emphasizes that both 18A and N2 utilize GAA transistors (RibbonFET), but the 1.8-nanometer node will adopt BSPND, a backside power delivery technology that optimizes power and clock. TSMC, on the other hand, believes that its N3P (3-nanometer) technology will rival Intel’s 18A in power consumption, performance, and area (PPA), while its N2 (2-nanometer) will surpass it in all aspects.

Additionally, Intel’s 20A manufacturing technology is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and backside power delivery network (BSPDN). These aim to achieve higher performance, lower power consumption, and increased transistor density.

Meanwhile, Intel’s 18A production node aims to further refine the innovations of 20A and provide additional PPA improvements from late 2024 to early 2025. Per Intel’s statements regarding its fab processes, its 2-nanometer technology is expected to be the earliest to debut.

Of particular note, Intel announced for the first time at the conference the development of 14A (1.4nm) and its evolutionary version, 14A-E. Intel’s 14A process is the industry’s first node to utilize ASML High-NA EUV lithography tools, making Intel the first company in the industry to acquire cutting-edge High-NA tools. Intel expects to develop 14A by 2027.

• Rapidus

In addition to the aforementioned semiconductor foundries, a Japanese company, Rapidus, is worth noting as well. Established in August 2022, Rapidus was jointly founded by eight Japanese companies including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND Flash giant Kioxia, and Mitsubishi UFJ.

On January 22nd of 2024, Rapidus President Junichi Koike announced during a press conference that construction of the Rapidus 2-nanometer chip fab in Japan is progressing smoothly, and the trial production line is scheduled to commence operations in April 2025 as planned. Additionally, there are plans for the construction of a second and third facility in the future.

In September of last year, Rapidus began construction of Japan’s first logic chip fab, “IIM-1,” in Chitose City, Hokkaido, capable of producing chips below 2 nanometers. It is reported that the fab is expected to be completed by December of this year.

Previously, Rapidus signed a collaboration agreement with IBM to develop technology based on IBM’s 2-nanometer process. IBM had already introduced the world’s first 2-nanometer process chip back in 2021. Similarly, IBM’s 2-nanometer process also utilizes GAA (Gate-All-Around) structure. This partnership provides Rapidus with the technical support necessary for advanced process development.

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• [News]The 2nm Semiconductor Foundry Race Between TSMC, Samsung, Rapidus Begins with an Equipment Battle

(Photo credit: TSMC)

In June 2023, leading processor manufacturer Intel reached an agreement with the German federal government, announcing the signing of an amended investment memorandum. The plan involves investing over EUR 30 billion to construct two new fabs in Magdeburg. The German federal government has agreed to provide a subsidy of EUR 10 billion, including incentives and subsidies from the European Chips Act and government initiatives.

According to a report by Tom’s Hardware citing sources, Intel has submitted conceptual drawings for a new fab in Germany. The initial plans include two fabs, designated as Fab 29.1 and Fab 29.2, equipped with the world’s most advanced semiconductor tools.

Moreover, Intel reportedly has ample space for up to six additional fabs. The first batch of two fabs is expected to commence operations in the fourth quarter of 2027, with both the Intel 14A (1.4nm) and Intel 10A (1nm) advanced processes believed to be part of the plan.

As per previous reports from TechNews, Intel has not disclosed any details regarding the 10A node, but it promises at least double-digit improvements in power consumption and performance. Intel CEO Pat Gelsinger has previously stated that new processes typically improve critical dimensions by approximately 14% to 15%. Therefore, it is plausible that the 10A and 14A nodes will also experience similar improvements.

Source: Intel

As per Intel’s roadmap, Intel 14A is also optimized in 2027, so it seems that 10A falls between 14A and 14A-E.

The report from Tom’s Hardware further indicates that Fab 29.1 and Fab 29.2, the two three-story buildings, occupy approximately 81,000 square meters, with a total length of 530 meters and a width of 153 meters. Each floor has a height ranging from 5.7 to 6.5 meters. Including the roof structure for air conditioning and heating, the building reaches a height of 36.7 meters.

The High-NA EUV exposure machines are installed on the second floor with a height of 6.5 meters, while the upper and lower floors are used for material logistics, providing necessary resources such as water, electricity, and chemicals.

ASML models that the 1st generation of the High-NA-enabled production node will employ between 4 to 9 High-NA EUV exposures and a total of 20 to 30 EUV exposures, encompassing both Low-NA and High-NA.

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• [News] Advancing into Intel 10A! Intel’s 2027 Blueprint Adds 1-Nanometer Process
• [News] Intel Promotes 1.8-Nanometer Process in South Korea, Reportedly Pledges Various Benefits to Startups

(Photo credit: Intel)

Intel’s foundry has extended its public roadmap, incorporating the Intel 14A process into the advanced process schedule and adding specific nodes. However, recent modifications to the roadmap have moved Intel 14A forward to 2026 and introduced a new process in 2027, namely 1 nanometer (Intel 10A).

According to TechNews citing reports from global media outlets tom’s Hardware and Extremetech, this marks Intel’s first announcement of the commencement of the 1-nanometer process. Although Intel had introduced Intel 10A at its exhibition, the news was restricted until now and has just been disclosed.

Intel 10A is set to enter the production/development (non-mass production) phase in 2027, while Intel 14A (1.4 nanometers) is scheduled for early production in 2026. Additionally, Intel is committed to constructing a fully autonomous AI-driven fab.

Keyvan Esfarjani, Intel’s Executive Vice President and General Manager of Manufacturing and Supply Chain, introduced the latest developments and showcased the technical roadmap. Intel plans to commence development of the 10A node by late 2027 to address gaps in EUV technology.

Assuming that Intel successfully launches its 1.8-nanometer process next year, follows with a 1.4-nanometer process in 2026, and then advances to 1-nanometer in 2027, Extremetech’s report claims that Intel is likely to be ahead of its competitor TSMC. TSMC estimates to begin its 2-nanometer process around 2025 or 2026, followed by a 1.4-nanometer process thereafter.

However, Intel has not disclosed any details regarding the 10A node, but it promises at least double-digit improvements in power consumption and performance. Intel CEO Pat Gelsinger has previously stated that new processes typically improve critical dimensions by approximately 14% to 15%. Therefore, it is plausible that the 10A and 14A nodes will also experience similar improvements.

Source: Intel

As per Intel’s roadmap, Intel 14A is also optimized in 2027, so it seems that 10A falls between 14A and 14A-E.

It is worth noting that according to Intel’s presentation notes, the final scale, speed, and process depend on commercial conditions and incentives, implying that funding from the U.S. Chip Act will affect expansion capacity.

Current Technological Developments at Intel

Intel’s 20A integrates two new technologies: backside power (PowerVIA) and GAA transistors (RibbonFET). Additionally, there is a proactive effort to enhance production capacity for advanced packaging technologies such as Foveros, EMIB, SiP (Silicon Photonics), and HBI (Hybrid Bond Interconnect).

Recently, Intel concluded all internal packaging for standard packaging, redirecting focus entirely towards high-end packaging, with standard packaging tasks now handled by OSATs (outsourced assembly and test companies).

While Intel’s 18A production base is located in Arizona, the location for manufacturing the 10A node has not been disclosed.

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• [News] Intel Promotes 1.8-Nanometer Process in South Korea, Reportedly Pledges Various Benefits to Startups
• [News] Samsung Secures 2-Nanometer Order from Japanese AI Startup Preferred Networks

(Photo credit: Intel)