“The Dawn of Generative AI Has Come!” This new chapter in the course of human technological evolution was first introduced by NVIDIA’s founder, Jensen Huang. Qualcomm’s CEO, Cristiano Amon, also shares this optimism regarding generative AI. Amon believes this technology is rapidly evolving and being adopted for applications such as mobile devices. It is expected to have the potential to radically transform the landscape of the smartphone industry. Similarly, Intel has declared the arrival of the “AI PC” era, signaling a major shift in computing-related technologies and applications.

This year, AI is transitioning from cloud computing to on-premise computing. Various “AI PCs” and “AI smartphones” are being introduced to the market, offering a wide range of selections. The current year of 2024 is even being referred to as the “Year of AI PC,” with brands such as Asus, Acer, Dell, Lenovo, and LG actively releasing new products to capture market share. With the rapid rise of AI PCs and AI smartphones, revolutionary changes are expected to occur in workplaces and people’s daily lives. Furthermore, the PC and smartphone industries are also expected to be reinvigorated with new sources of demand.

An AI PC refers to a laptop (notebook) computer capable of performing on-device AI computations. Its main difference from regular office or business laptops lies in its CPU, which includes an additional neural processing unit (NPU). Examples of AI CPUs include Intel’s Core Ultra series and AMD’s Ryzen 8040 series. Additionally, AI PCs come with more DRAM to meet the demands of AI computations, thereby supporting related applications like those involving machine learning.

Microsoft’s role is crucial in this context, as the company has introduced a conversational AI assistant called “Copilot” that aims to seamlessly integrate itself into various tasks, such as working on Microsoft Office documents, video calls, web browsing, and other forms of collaborative activities. With Copilot, it is now possible to add a direct shortcut button for AI on the keyboard, allowing PC users to experience a holistic collaborative relationship with AI.

In the future, various computer functions will continue to be optimized with AI. Moreover, barriers that existed for services such as ChatGPT, which still require an internet connection, are expected to disappear. Hence, AI-based apps on PCs could one day be run offline. Such a capability is also one of the most eagerly awaited features among PC users this year.

Surging Development of LLMs Worldwide Has Led to a Massive Increase in AI Server Shipments

AI-enabled applications are not limited to PCs and smartphones. For example, an increasing number of cloud companies have started providing services that leverage AI in various domains, including passenger cars, household appliances, home security devices, wearable devices, headphones, cameras, speakers, TVs, etc. These services often involve processing voice commands and answering questions using technologies like ChatGPT. Going forward, AI-enabled applications will become ubiquitous in people’s daily lives.

Not to be overlooked is the fact that, as countries and multinational enterprises continue to develop their large language models (LLMs), the demand for AI servers will increase and thus promote overall market growth. Furthermore, edge AI servers are expected to become a major growth contributor in the future as well. Small-sized businesses are more likely to use LLMs that are more modest in scale for various applications. Therefore, they are more likely to consider adopting lower-priced AI chips that also offer excellent cost-to-performance ratios.

TrendForce projects that shipments of AI servers, including models equipped with GPUs, FPGAs, and ASICs, will reach 1.655 million units in 2024, marking a growth of 40.2% compared with the 2023 figure. Furthermore, the share of AI servers in the overall server shipments for 2024 is projected to surpass 12%.

Regarding the development of AI chips in the current year of 2024, the focus is on the competition among the B100, MI300, and Gaudi series respectively released by NVIDIA, AMD, and Intel. Apart from these chips, another significant highlight of this year is the emergence of in-house designed chips or ASICs from cloud service providers.

In addition to AI chips, the development of AI on PCs and smartphones is certainly another major driving force behind the technology sector in 2024. In the market for CPUs used in AI PCs, Intel’s Core Ultra series and AMD’s Ryzen 8000G series are expected to make a notable impact. The Snapdragon X Elite from Qualcomm has also garnered significant attention as it could potentially alter the competitive landscape in the near future.

Turning to the market for SoCs used in AI smartphones, the fierce competition between Qualcomm’s Snapdragon 8 Gen 3 and MediaTek’s Dimensity 9300 series is a key indicator. Another development that warrants attention is the adoption of AI chips in automotive hardware, such as infotainment systems and advanced driver assistance systems. The automotive market is undoubtedly one of the main battlegrounds among chip suppliers this year.

The supply chain in Taiwan has played a crucial role in providing the hardware that supports the advancement of AI-related technologies. When looking at various sections of the AI ecosystem, including chip manufacturing as well as the supply chains for AI servers and AI PCs, Taiwan-based companies have been important contributors.

Taiwan-based Companies in the Supply Chain Stand Ready for the Coming Wave of AI-related Demand

In the upstream of the supply chain, semiconductor foundries and OSAT providers such as TSMC, UMC, and ASE have always been key suppliers. As for ODMs or OEMs, companies including Wistron, Wiwynn, Inventec, Quanta, Gigabyte, Supermicro, and Foxconn Industrial Internet have become major participants in the supply chains for AI servers and AI PCs.

In terms of components, AI servers are notable for having a power supply requirement that is 2-3 times greater than that of general-purpose servers. The power supply units used in AI servers are also required to offer specification and performance upgrades. Turning to AI PCs, they also have higher demands for both computing power and energy consumption. Therefore, advances in the technologies related to power supply units represent a significant indicator this year with respect to the overall development of AI servers and AI PCs. Companies including Delta Electronics, LITE-ON, AcBel Polytech, CWT, and Chicony are expected to make important contributions to the upgrading and provisioning of power supply units.

Also, as computing power increases, heat dissipation has become a pressing concern for hardware manufacturers looking to further enhance their products. The advancements in heat dissipation made by solution providers such as Sunon, Auras, AVC, and FCN during this year will be particularly noteworthy.

Besides the aforementioned companies, Taiwan is also home to numerous suppliers for other key components related to AI PCs. The table below lists notable component providers operating on the island.

With the advent of generative AI, the technology sector is poised for a boom across its various domains. From AI PCs to AI smartphones and a wide range of smart devices, this year’s market for electronics-related technologies is characterized by diversity and innovation. Taiwan’s supply chain plays a vital role in the development of AI PCs and AI servers, including chips, components, and entire computing systems. As competition intensifies in the realm of LLMs and AI chips, this entire market is expected to encounter more challenges and opportunities.

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(Photo credit: Qualcomm)

As Moore’s Law progresses, transistors are becoming smaller and denser, with more layers stacked on top of each other. This may require passing through 10 to 20 layers of stacking to provide power and data signals to the transistors below, leading to increasingly complex networks of interconnects and power lines. Simultaneously, as electrons transmit downward, IR drop phenomena occur, resulting in power loss.

Apart from power loss, the occupation of space by power supply lines is also a concern, which often occupies at least 20% of resources. Addressing the issue of signal network and power supply network resource contention to miniaturize components becomes a major challenge for chip designers. As per a report from TechNews, this has led the semiconductor industry to begin shifting power supply networks to the backside of chips.

• TSMC’s Super Rail Technology Set to Revolutionize Chip Efficiency with A16 Process Node Debut in 2025

Leading semiconductor foundry TSMC recently unveiled its A16 process at a technical forum in North America.

This new node not only accommodates more transistors, enhancing computational efficiency, but also reduces energy consumption. Of particular interest is the integration of the Super PowerRail architecture and nanosheet transistors in the A16 chip, driving the development of data center processors that are faster and more efficient.

Notably, TSMC’s A16 employs a different chip wiring manner, with power wires delivering electricity to transistors located beneath rather than above them, known as backside power supply, facilitating the production of more efficient chips.

In fact, one of the methods to optimize processors is to alleviate IR drop, a phenomenon that reduces the voltage received by the transistors on the chip, consequently affecting performance. The A16 wiring is less prone to voltage drops, simplifying power distribution and allowing for tighter chip packaging, aiming to accommodate more transistors to enhance computational capabilities.

Additionally, TSMC’s A16 process technology directly connects the power transmission lines to the source and drain of the transistor, which improves chip efficiency.

Using the Super PowerRail in A16, TSMC achieves an 10% higher clock speed or a 15% to 20% decrease in power consumption at the same operating voltage (Vdd) compared to N2P. Moreover, the chip density is increased by up to 1.10 times, supporting data center products.

• Intel’s PowerVia Set for Production on Intel 20A in 2024

Similar to TSMC’s Super PowerRail, Intel has also introduced its backside power delivery solution, PowerVia.

According to Intel, power lines typically occupy around 20% of the space on the chip surface, but PowerVia’s backside power delivery technology saves this space, allowing  more flexibility in the interconnect layers.

In addition, the Intel team previously created the Blue Sky Creek test chip to demonstrate the benefits of backside power delivery technology. Test results indicated that most areas of the chip achieved over 90% cell utilization, with a 30% platform voltage droop improvement, 6% frequency benefit, increased unit density, and potential cost reduction. The PowerVia test chip also exhibited excellent heat dissipation properties, aligning with expectations for higher power density as logic shrinks.

Furthermore, PowerVia is slated to be integrated into Intel Foundry Services (IFS), enabling faster achievement of product efficiency and performance enhancements for customer-designed chips.

According to official documentation from Intel, the tech giant plans to implement PowerVia on Intel 20A process technology along with the RibbonFET architecture for the full-surround gate transistor. Production readiness is expected in the first half of 2024, with initial steps being taken at the fabrication plant for future mass production of client ARL platforms.

• Samsung Plans to Implement SF1.4 Process by 2027

In addition to leading the transition to GAA transistor technology, Samsung, another competitor of TSMC, is also wielding its Backside Power Delivery Network as a key weapon in the pursuit of advanced processes.

According to a previous report from Samsung, Jung Ki-tae Jung, Chief Technology Officer of Samsung’s foundry division, announced plans to apply the backside power delivery technology to the 1.4-nanometer process by 2027.

Reports from Korean media outlet theelec indicate that compared to traditional front-end power delivery networks, Samsung’s backside power delivery network successfully reduces wafer area consumption by 14.8%, providing more space on the chip to accommodate additional transistors, thereby enhancing overall performance.

Additionally, wiring length is reduced by 9.2%, aiding in resistance reduction to allow more current flow, leading to lower power consumption and improved power transmission conditions. Samsung Electronics representatives noted that the mass production timeline for semiconductor chips adopting backside power delivery technology may vary depending on customer schedules, and Samsung is currently investigating customer demand for the application of this technology.

Read more

• [News] More Complex than Intel’s? TSMC’s Super PowerRail – Elevating Chip Performance through Advanced Power Delivery
• [News] Battle of the Titans in the Angstrom Era – TSMC’s A16 Competes with Intel’s 14A and Samsung’s SF1.4

According to a report from Nikkei News, US chip giant Intel will join forces with 14 Japanese companies to develop automation technology for “backend” semiconductor processes such as packaging. The aim is said to achieve automation by 2028, highlighting efforts by both the US and Japan to collaborate and reduce geopolitical risks in the semiconductor supply chain.

Intel’s collaborating partners include Japanese firms such as Omron, Yamaha Motor, Resonac, and Shin-Etsu Polymer, a subsidiary of Shin-Etsu Chemical Industry. The alliance, led by Intel Japan’s Managing Director Kunimasa Suzuki, plans to invest hundreds of billions of Japanese Yen in research and development, aiming to demonstrate technological achievements before 2028.

In the semiconductor field, as “frontend” process technologies such as circuit formation approach physical limits, the focus of technological competition is gradually shifting to “backend” processes such as chip stacking to enhance performance.

Most semiconductor backend processes are currently carried out through manual labor, leading to the concentration of factories in China and Southeast Asian countries with abundant labor force. However, to establish plants in countries like the US and Japan, where labor costs are higher, industry players consider automation technology as a crucial prerequisite.

Led by Intel, the alliance plans to establish backend production lines in Japan in the coming years, aiming for full automation. They also intend to standardize backend technologies to manage and control manufacturing, inspection, and equipment processing procedures under a single system.

According to data from the Japanese Ministry of Economy, Trade and Industry, Japanese companies currently hold a 30% share of the global semiconductor production equipment market and dominate approximately half of the semiconductor materials market.

It is widely expected that the Japanese Ministry of Economy, Trade and Industry will allocate hundreds of billions of Japanese Yen in subsidies for this project. The Japanese government has allocated approximately JPY 4 trillion (around USD 26 billion) from fiscal year 2021 to 2023 to support key industries contributing to economic security.

In April of this year, Japan approved a subsidy of JPY 53.5 billion to Rapidus to assist in backend technology development. Additionally, there are considerations to offer incentives to attract global backend capacity providers to establish operations in Japan.

Japanese and American policymakers are attempting to keep most of the chip manufacturing processes within their own territories, aiming to reduce risks in critical supply chains.

TrendForce has previously reported that Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

Read more

• [News] Overseas Expansion of Testing and Packaging Facilities – Japan, Malaysia, and Singapore Emerge as Top Choices
• [News] Rapidus Focuses on Small Clients, Diversifies into Japan to Mitigate US Geopolitical Risks

(Photo credit: Intel)

Per a report from TechNews, during Intel’s earnings call last week, CEO Pat Gelsinger stated that the supply of Core Ultra processors in the second quarter is limited due to insufficient wafer-level assembly capacity.

Gelsinger mentioned in the meeting that with the increasing demand for AI PCs and customers continually adding processor orders to Intel due to Windows update cycles, Intel’s AI PC CPU shipments for 2024 are expected to surpass the originally set target of 40 million units. In response, Intel is actively ramping up production to meet customer demand, with the current supply bottleneck primarily concentrated in the backend wafer-level assembly.

Wafer-level assembly is a technology where packaging is done on wafers before they are cut into chips, widely utilized in processors like Meteor Lake and future Core Ultra processors. However, in the face of overwhelming demand, this production bottleneck has led Intel’s Consumer Computing Division to anticipate second-quarter revenue to be roughly equivalent to that of the first quarter, around USD 7.5 billion.

To address this issue, Intel is actively enhancing its wafer-level assembly capacity to meet the growing orders. It is expected that the current tight situation will be alleviated in the second half of 2024, facilitating further revenue growth for the Consumer Computing Division.

As per previous report by Economic Daily News, Intel has advanced packaging capacity in Oregon and New Mexico in the United States and is actively expanding its advanced packaging capabilities in its new facility in Penang. It is noteworthy that Intel once stated its intention to offer customers the option to only use its advanced packaging solutions, expected to provide customers with greater production flexibility.

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• [News] From Technical Prowess to Integration Capability, TSMC and Intel Target Advanced Packaging to Seize Ecosystem Opportunities
• [News] NVIDIA Expands Advanced Packaging Supply Chain with Intel’s Inclusion, Diverting Orders from TSMC

(Photo credit: Intel)

TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

Read more

• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News] Intense Competition with Samsung and Intel in Advanced Processes; TSMC Speeds Up 2nm Progress