Intel announced on the evening of January 25th that it will collaborate with UMC to develop 12-nanometer process platform technology. The production will utilize Intel’s wafer fab capacity in the United States, and both parties will share the cash generated from the collaboration. The production is expected to commence in 2027.

This marks Intel’s first collaboration with a Taiwanese foundry in process development. Intel is actively venturing into the foundry business, and this collaboration with UMC not only marks a new milestone in the Taiwan-US semiconductor foundry industry but also initiates a new competitive relationship in the global foundry industry.

Intel and UMC have not disclosed the expected investment amount for their collaboration. UMC stated that the investment amount cannot be disclosed as the collaborative technology will not enter production until 2027, at which point it will begin contributing to revenue.

Therefore, the investment will be shared by both parties. Regarding whether they will advance towards more advanced processes, UMC stated that they do not respond to distant matters and primarily focus on financial indicators that the company can afford.

Intel noted that the collaboration with UMC to develop the 12-nanometer process platform is primarily aimed at addressing the high growth in markets such as mobile, communication infrastructure, and networking.

This long-term collaboration combines Intel’s large-scale manufacturing capacity in the United States with UMC’s extensive experience in mature processes in foundry, expanding the process portfolio while providing a better regionally diversified and resilient supply chain to assist global customers in making better procurement decisions.

The new process node, according to Intel, will be developed and manufactured in Fabs 12, 22 and 32 at Intel’s Ocotillo Technology Fabrication site in Arizona.

“Taiwan has been a critical part of the Asian and global semiconductor and broader technology ecosystem for decades, and Intel is committed to collaborating with innovative companies in Taiwan, such as UMC, to help better serve global customers,” said Stuart Pann, Intel senior vice president and general manager of Intel Foundry Services (IFS).

He further stated that, “Intel’s strategic collaboration with UMC further demonstrates our commitment to delivering technology and manufacturing innovation across the global semiconductor supply chain and is another important step toward our goal of becoming the world’s second-largest foundry by 2030.”

Jason Wang, UMC co-president, said that UMC’s collaboration with Intel on a U.S.-manufactured 12 nm process with FinFET capabilities in the United States is a crucial aspect of the company’s pursuit of cost-effective capacity expansion and technological node advancement.

UMC anticipates that this collaboration will assist customers in smoothly migrating to this critical node while benefiting from the resilience of the expanded capacity in the North American market.

UMC looks forward to strategic collaboration with Intel, leveraging the complementary advantages of both parties to expand potential markets and significantly accelerate technology development timelines.

TrendForce believes that this partnership, which leverages UMC’s diversifed technological services and Intel’s existing factory facilities for joint operation, not only aids Intel in transitioning from an IDM to a foundry business model, it also allows UMC to agilely leverage FinFET capacity without the pressure of heavy capital investments.

TrendForce forecasts that this collaboration slashes average investment by a staggering 80%, compared to the cost of new equipment. This calculation includes only the expenses related to the relocation of equipment, secondary piping costs for factory services, and other minor associated expenses for ancillary equipment.

However, the journey is not without its challenges. UMC’s 14nm process, in development since 2017, is yet to hit mass production, and its 12nm process is still in the R&D phase, with mass production eyed for late 2026. This collaboration’s mass production timeline is tentatively set for 2027, with the FinFET architecture’s stability under careful watch.

Overall, TrendForce views this alliance as a significant step. UMC brings its plentiful experience in mature processes, while Intel contributes its advanced technological prowess.

This partnership is not just about mutual benefits in the 10nm process level; it’s a watchpoint for potentially deeper and more extensive collaboration in their respective fields of expertise. In the dynamic world of semiconductor manufacturing, this Intel-UMC alliance is a fascinating development to keep an eye on.

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(Photo credit: Intel)

According to the report from TechNews, Intel CEO Pat Gelsinger, speaking at the World Economic Forum, stated that export sanctions from the United States, Japan, and the Netherlands are temporarily limiting China’s development in semiconductor processes below 7 nanometers.

Despite China’s ongoing efforts to advance its semiconductor industry and design more sophisticated chip manufacturing tools, it still lags behind the global semiconductor industry by approximately ten years, and Gelsinger believes this gap will persist.

Gelsinger suggests that to some extent, the policies of the United States, Japan, and the Netherlands set a threshold of 10 to 7 nanometers for China’s semiconductor industry. Currently, SMIC has 7-nanometer technology, lagging approximately five and a half years behind TSMC and Samsung. Shanghai Huali Microelectronics (HLMC) began trial production based on 14-nanometer FinFET process in 2020, trailing TSMC by nine to ten years.

Both SMIC and HLMC utilize manufacturing equipment and materials from the Netherlands, Japan, South Korea, Taiwan, and the United States. However, due to the unavailability of these raw materials, Chinese companies have had to develop their own wafer fab equipment and find methods for purifying gases, resists, and other chemicals used in advanced chip manufacturing.

Gelsinger estimates that China’s semiconductor industry lags behind the global standard by about ten years and, although it will continue to develop, he foresees this gap persisting for the next decade. Given the highly interconnected nature of the semiconductor industry, encompassing companies like Zeiss, ASML, Japanese chemical suppliers, and Intel for mask manufacturing, he believes that this cumulative difference amounts to a ten-year gap and will continue to do so under export policies.

If China cannot acquire advanced chip equipment and technology, Chinese semiconductor companies might attempt to narrow the gap with the global semiconductor industry through reverse engineering and replication. While not a sustainable approach, it may be the only choice available.

Regarding advanced processes, Gelsinger also mentioned that Intel is actively developing technologies below 2 nanometers and is looking beyond to 1.5 nanometers, stating, “We are racing to go below 2nm and then 1.5nm, and you know we see no end to that in sight.”

(Image: Intel)

TSMC announced during its briefing on the 18th that, due to robust demand in the 2-nanometer market, it plans to add another fab to the initially planned two fabs in Kaohsiung.

The company intends to use the 2-nanometer process for all three fabs in Kaohsiung, in addition to the originally planned 2-nanometer fab in Hsinchu’s Baoshan. Furthermore, the land recently acquired in Hsinchu Science Park will also be designated for a 2-nanometer fab. This reflects the strong preference for the 2-nanometer process among customers and underscores TSMC’s confidence in its in-house 2-nanometer process technology.

According to a report by TechNews following the briefing on the 18th, TSMC’s CFO Wendell Huang, stated in a media gathering that the strong demand in the high-performance computing and smartphone markets prompted the decision to increase the number of fabs in Kaohsiung from the originally planned two to three. Once the three 2-nanometer fabs are in full production, Kaohsiung will become a crucial manufacturing hub for TSMC’s 2-nanometer process.

In addition, with the recent approval from the Ministry of the Interior’s Urban Planning Commission, the land in Hsinchu Science Park designated for TSMC’s use, expected to be available in June 2024, is also being planned for a 2-nanometer fab.

Recent market reports suggest that TSMC, the leading semiconductor foundry, is set to proceed as scheduled with its plan to adopt the GAA (Gate-All-Around) architecture from the 2-nanometer process onward.

The P1 wafer fab in Baoshan, located in the Hsinchu Science Park, is anticipated to begin equipment installation as early as April 2024, while the Kaohsiung fab is projected to commence production using the GAA architecture for the 2-nanometer process technology in 2025.

Furthermore, in response to Intel securing the first High-NA EUV exposure equipment from ASML for its 18A advanced process, TSMC has indicated that it is also planning for High-NA EUV exposure equipment. However, the current timeline anticipates engineering verification of the High-NA EUV exposure equipment in 2024, with gradual integration into the manufacturing process set to follow.

(Image: TSMC)

The global foundry advanced process battle is reigniting, as reported by the Commercial Times. TSMC’s 2-nanometer process at the Baoshan P1 wafer fab in Hsinchu is set to commence equipment installation as early as April, incorporating a new Gate-All-Around (GAA) transistor architecture and aiming for mass production in 2025.

Additionally, expansion plans for Baoshan P2 and the Kaohsiung fab are projected to join in 2025, with evaluations underway for Phase 2 in the Central Taiwan Science Park. The competition with Samsung and Intel in the most advanced process is intensifying.

Semiconductor industry sources note the ongoing progress in global foundry advanced processes, with Samsung entering GAA architecture early at 3 nanometers, though facing yield challenges, while Intel anticipates mass production of its RibbonFET architecture at 20A this year.

In response to fierce competition, TSMC must accelerate its pace. The ‘Gate-All-Around’ (GAA) technology is a critical factor determining whether chip processing power will double within 1.5 to 2 years.

As per the report, Samsung’s attempt to lead in the 3-nanometer chip segment, transitioning from traditional FinFET, has faced stability issues in yield, hampering customer adoption, and giving TSMC confidence in its 3-nanometer progress. This also highlights the increased complexity in transitioning from 2D to 3D chip designs with GAA transistor architecture.

Furthermore, Intel is intensifying its efforts to catch up, planning to launch Intel 20A in the first half of the year and Intel 18A in the second half. However, it is speculated that Intel 20A will be exclusively used for Intel’s own products, maintaining a close collaboration with TSMC.

TSMC, adopting a cautious approach, benefits from a more advantageous cost structure by minimizing changes in production tools within the same process technology and manufacturing flow. For customers, altering designs during advanced process development incurs significant time and economic costs.

Supply chain sources reveal that TSMC finalized various parameters for its 2-nanometer process at the end of last year, confirming specialty gases and equipment. Contracts are gradually being signed, with equipment installation at the Baoshan P1 fab scheduled to commence in April. Equipment industry sources suggest that TSMC’s process advancement is progressing rapidly as expected, speculating that there will be updates on the Baoshan P2 fab later this year.

(Image: TSMC)

On January 9th, Intel unveiled its latest automotive AI chips, entering into direct competition with rivals NVIDIA and Qualcomm in the automotive chip market. In a bid to strengthen its position, Intel also announced the acquisition of automotive chip company Silicon Mobility.

Reportedly, Intel stated that Silicon Mobility, a French startup, specializes in designing System-on-a-Chip (SoC) technology for controlling electric vehicle motors and in-car charging systems, along with software. The acquisition amount was not disclosed by Intel.

As per Reuter citing from Intel’s automotive business chief Jack Weast, he has indicated that, intel’s new automotive system on a chip products will adapt the company’s recently launched AI PC technology for the durability and performance requirements of vehicles.

Weast further clarified, “Intel will not require automakers to use advanced driving chips designed by its former Mobileye unit, he said. Instead, automakers can have Intel incorporate their own chiplets to enable specific functions into the Intel system at a lower cost.”

Intel’s chips designed for infotainment systems are already integrated into 50 million vehicles. As the automotive chip market continues to expand, the demands on chips are increasing, covering technologies such as autonomous driving, upgradable in-car system software, and complex dashboard displays amid strong competition from NVIDIA and Qualcomm.

Weast has addressed ahead of the CES technology show in Las Vegas that Chinese automaker Zeekr will be the first automaker to use Intel’s AI system on a chip to create “an enhanced living room experience” in vehicles, including AI voice assistants and video conferencing. Zeekr, an electric vehicle brand under the Geely Holding Group, is a customer of both Intel and NVIDIA.

Intel will try to separate itself from rivals by offering chips that automakers can use across their product lines, from lowest-priced to premium vehicles, Weast said.

According to Reuter, Weast addressed reporters in a conference call before the announcement at the CES technology show in Las Vegas, stating, “Intel has done a pretty terrible job communicating our success in automotive, We are going to change that.”

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(Photo credit: Intel)