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Intel, Qualcomm, Google, and other tech giants are reportedly joining forces with over a hundred startups to challenge NVIDIA’s dominance in the market, as per a report from Reuters. Reportedly, their goal is to collectively penetrate the artificial intelligence (AI) software domain, guiding developers to migrate away from NVIDIA’s CUDA software platform.
NVIDIA’s CUDA is a parallel computing platform and programming model designed specifically to accelerate GPU computing. It allows GPU users to fully leverage their chip’s computational power in AI and other applications. As per a previous report from TrendForce, since 2006, NVIDIA has introduced the CUDA architecture, nearly ubiquitous in educational institutions. Thus, almost all AI engineers encounter CUDA during their academic tenure.
However, tech giants are now reportedly aiming to disrupt the current status quo. According to a report from Reuters on March 25th, Intel, Qualcomm, and Google are teaming up to challenge NVIDIA’s dominant position. They plan to provide alternative solutions for developers to reduce dependence on NVIDIA, encourage application migration to other platforms, and thereby break NVIDIA’s software monopoly and weaken its market influence.
The same report from Reuters further indicated that several tech companies have formed the “UXL Foundation,” named after the concept of “Unified Acceleration” (UXL), which aims to harness the power of acceleration computing using any hardware.
The project plans to leverage Intel’s oneAPI technology to develop software and tools supporting multiple AI accelerator chips. The goal is to reduce the technical barriers developers face when dealing with different hardware platforms, streamline the development process, enhance efficiency, and accelerate innovation and application of AI technology.
Vinesh Sukumar, Head of AI and Machine Learning Platform at Qualcomm, stated, “We’re actually showing developers how you migrate out from an NVIDIA platform.”
Bill Magro, Head of High-Performance Computing at Google, expressed, “It’s about specifically – in the context of machine learning frameworks – how do we create an open ecosystem, and promote productivity and choice in hardware.” The foundation is said to aim to finalize technical specifications in the first half of this year and strives to refine technical details by the end of the year.
However, CUDA software has established a solid foundation in the AI field, making it unlikely to be shaken overnight. Jay Goldberg, CEO of financial and strategic advisory firm D2D Advisory, believes that CUDA’s importance lies not only in its software capabilities but also in its 15-year history of usage. A vast amount of code has been built around it, deeply ingraining CUDA in numerous AI and high-performance computing projects. Changing this status quo would require overcoming significant inertia and dependency.
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(Photo credit: NVIDIA)
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Benefited from frequent orders from its top three clients, Apple, Intel, and AMD, strong momentum has reportedly been driven for TSMC’s 3-nanometer orders, as per a report from Economic Daily News. Anticipated to see sequential growth throughout the year, these orders are expected to remain robust until the end of the year, positioning TSMC as a leader in the semiconductor industry’s recovery.
TSMC has a longstanding policy of not commenting on customer order dynamics. However, it is cited in the report that in the fourth quarter of last year, 3-nanometer orders accounted for approximately 15% of its revenue. With the adoption of 3-nanometer production by major clients this year, revenue from 3-nanometer orders is expected to surpass 20%, becoming the second-largest revenue contributor, following only the 5-nanometer process.
Looking at the orders placed by the top three clients for the 3-nanometer process, Apple is set to introduce the A18 series processor in its iPhone 16 lineup this year. Additionally, the latest self-developed M4 chip for laptops will also be produced by TSMC using the 3-nanometer process, starting in the second quarter.
On the Intel side, the Lunar Lake central processor, graphics processor, and high-speed IO chip are all confirmed to begin mass production at TSMC in the second quarter. This marks Intel’s first instance of outsourcing its entire mainstream consumer platform chip series to TSMC, making it a significant new source of orders for TSMC’s 3-nanometer process this year.
AMD, on the other hand, is poised to unveil its new Zen 5 architecture platform under the code name “Nirvana” this year, expected to significantly enhance AI applications. Following its customary practice, AMD will utilize TSMC’s wafer foundry services, with production set to commence on the 3-nanometer process and an expected launch in the latter half of the year.
TSMC, reportedly, is expanding its production capacity for the 3nm family and advanced packaging this year to meet the large orders from major clients such as Apple, NVIDIA, and AMD in the coming years.
As per TrendForce’s data, the 3nm process alone contributed 6% to TSMC’s Q3 revenue, with advanced processes (≤7nm) accounting for nearly 60% of its total revenue.
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(Photo credit: TSMC)
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The US-China tech war continues to escalate, as reported by the Financial Times (FT). Beijing has reportedly instructed official institutions in China to refrain from using PCs and servers equipped with microprocessors from Intel and AMD, as well as to reduce procurement of Microsoft Windows operating systems and database software outside of China.
In response to these reports, both Microsoft and Intel have declined to comment, while AMD, China’s Ministry of Finance, Ministry of Industry and Information Technology, and the China Information Security Evaluation Center have not responded to requests for comment from FT reporters.
FT further reveals that Chinese authorities have requested state-owned enterprises to promote localization internally. Intel and AMD are the two major semiconductor giants in the United States, dominating nearly all global market shares of PC processors.
As both Intel and AMD are significant customers of TSMC’s advanced process nodes, this move is expected to influence TSMC’s future order status. Regarding China’s full-scale development of proprietary computer processors, its potential impact on ASIC-related companies in Taiwan remains to be seen.
As per Industry sources cited by the report, they have suggested that this move by Chinese authorities demonstrates their determination to strengthen local semiconductor autonomy and enhance manufacturing and design capabilities. On the manufacturing side, the focus remains on supporting SMIC, while chip design is primarily led by companies such as Huawei and Phytium.
Per the same report, following the release of new guidelines by China’s Ministry of Finance and Ministry of Industry and Information Technology on December 26th last year, officials have begun adhering to the latest standards for PC, laptop, and server procurement this year. They have mandated that government departments at the township level and above, as well as party organizations, must incorporate standards for purchasing “secure and trustworthy” processors and operating systems.
The China Information Technology Security Evaluation Center has published the first list of “safe and reliable” processors and operating systems, all of which are from Chinese enterprises.
Among the 18 approved processors are chips from Huawei and Phytium. Chinese processor manufacturers are utilizing a hybrid architecture combining Intel x86, Arm, and self-developed designs for chip production, while operating systems are sourced from open-source Linux software.
Prior to the speculated tightening of restrictions by China on the United States, a report from Bloomberg citing sources had already signaled that the US government is considering adding Chinese semiconductor companies linked to Huawei to a blacklist.
Currently, companies that have been listed on the entity list by the US Department of Commerce include Huawei, SMIC (Semiconductor Manufacturing International Corporation), and Shanghai Micro Electronics. Additionally, China’s other major memory manufacturer, Yangtze Memory Technology Corp, was added to this restriction list in 2022.
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As TSMC and Intel slow down their plans for building fabs in the United States, the supply chain, according to a report from Nikkei Asia, is also said to delay in following suit, with semiconductor material suppliers like Topco Scientific, LCY Chemical, and Chang Chun Group among those named.
Per the same report citing statements from several industry sources, the construction of these fabs has been either postponed or significantly scaled back due to soaring costs of construction materials and labor, as well as a shortage of construction workers.
While some delays may be temporary, other fab construction projects are being thoroughly reassessed, with no specific timetable for resuming. Suppliers attribute the delays in fab construction plans to the slower-than-expected progress of Intel and TSMC in setting up their facilities.
The sources cited in the report also revealed that Solvay, a leading supplier of high-purity hydrogen peroxide for semiconductor use based in Belgium, has postponed the construction of its Arizona plant due to cost concerns and fears that Intel and TSMC’s expansion progress may take longer than expected.
Meanwhile, another major manufacturer of high-purity hydrogen peroxide for semiconductors, Taiwan’s Chang Chun Group, has significantly scaled back the construction of its new Arizona plant due to costs that have exceeded expectations by several times.
Regarding this issue, Chang Chun Group reportedly opted not to provide comments, while Solvay mentioned they are currently investigating the matter.
Topco Scientific has reportedly pointed out that it has acquired land in Arizona, USA. However, the company is currently adjusting its investment schedule for warehouse logistics in Arizona. This adjustment aligns with the progress and demand of its customers in setting up factories, as well as the local infrastructure planning, which includes water and power supply and road construction.
Per the report citing sources, TSMC originally planned to begin mass production at its Arizona plant in 2024. However, this timeline has now been postponed to 2025. Initial expectations for the second fab’s schedule were set for 2026, but it is now likely to be pushed back to 2027-2028
As per a previous report from TechNews, despite the United States outperforms Taiwan in various aspects for foundry construction, the primary obstacle is regulatory issues.
Due to the unique federal structure of the United States, foundry construction must comply with federal, state, and local regulations, resulting in an exceptionally complex regulatory process. Additionally, environmental policies pose obstacles to foundry construction, particularly due to stringent requirements for environmental protection
The report suggests that to enhance the United States’ competitiveness in the global semiconductor industry, the government needs to streamline regulatory processes, eliminate redundant regulations, and establish expedited pathways to accelerate semiconductor industry construction projects.
Additionally, there should be an acceleration of environmental review processes and investment in the development of alternative materials to ensure sustainable semiconductor material supplies.
With the continued growth in global semiconductor demand, the construction speed and efficiency of US semiconductor fabs will directly impact its position in the global market.
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Driven by the AI chip wave, “advanced packaging” emerges as the hottest technology in the semiconductor industry. Its significance extends beyond computational power demands, as the escalating cost of semiconductor processes and the limits of Moore’s Law make the “integration capability” of advanced packaging a crucial weapon for industry players to break through.
According to a report from TechNews, TSMC, Intel, and Samsung have all been deeply involved in advanced packaging for many years and have already introduced corresponding solutions. However, these semiconductor giants are not only focused on this aspect.
In addition to their own technologies, they are actively fostering supply chains, setting standards, and building ecosystems. By accelerating the development of advanced packaging technology, they are also laying the groundwork for their future influence.
Intel, for instance, has chosen to start with standardization by proposing the Universal Chiplet Interconnect Express (UCIe) alliance. Through open specifications and standardized connections, the protocol directly adopts mature standards like PCI Express (PCIe) and the recently developed Compute Express Link (CXL).
The reason for starting with chiplet technology is that in recent years, more and more semiconductor companies have discovered that designing chips using Chiplet architecture and integrating them through advanced packaging technology is more cost-effective than traditional System-on-Chip (SoC) approaches.
Therefore, Intel’s focus on connecting chiplets through standards like UCIe is aimed at providing a standardized interface stack for complete chiplet integration. UCIe supports 2D, 2.5D, and bridge packaging, with future development expected to include support for 3D packaging as well.
Intel’s Packaging Test Technology Development Department’s Senior Chief Engineer, Zhiguo Qian, directly involved in the UCIe Alliance, emphasizes that advanced packaging has become a crucial aspect of semiconductor development, particularly in ensuring the continuation of Moore’s Law.
Qian further points out that when considering the impact of the UCIe standard on the advanced packaging industry, it indeed establishes a standard for interconnecting chiplets within SoCs. This was the original intent behind Intel’s promotion of the UCIe standard alliance.
Currently, advanced packaging is mostly divided into different structures like 2.5D and 3D, and some even classify it as 2.1D or 2.2D, showcasing diverse structural designs across the industry.
However, within these structures, each company has its own proprietary interface solutions, and some even offer multiple solutions. Therefore, to meet customer demands, these standard interconnections must not only be at the forefront of technology but also be compatible with various standards that are open and do not incur any licensing fees.
On the other hand, the UCIe alliance has established various standards, such as the required packaging architectures and interface wiring designs, to achieve the desired performance levels. These standards provide guidelines for customers seeking advanced packaging solutions. By adhering to UCIe standards, customers can anticipate the performance of their chips, without the need for trial and error(in the IC designing stage).
Currently, companies participating in the UCIe alliance include Qualcomm, AMD, Arm, NVIDIA, TSMC, ASE Group, Winbond Electronics, and Applied Materials, among others, along with semiconductor giants like Samsung. Additionally, Google Cloud, Microsoft, and Meta are members, alongside over 120 other companies.
TSMC is also focused on ecosystem development, as evidenced by its announcement of the 3DFabric Alliance within the Open Innovation Platform (OIP) during the 2022 Open Innovation Platform Ecosystem Forum.
In fact, the 3DFabric Alliance is built upon TSMC’s 3DFabric technology introduced in 2020. This technology encompasses a comprehensive solution ranging from advanced processes to silicon stacking and advanced packaging technologies such as CoWoS and InFO.
With an established customer base for its 3DFabric technology, TSMC expanded it into an alliance in 2022. The goal is to assist customers in achieving rapid implementation of chip and system-level innovations while strengthening TSMC’s influence in advanced packaging.
The 3DFabric Alliance marks TSMC’s sixth open innovation platform alliance and is the semiconductor industry’s first alliance aimed at accelerating innovation and enhancing the 3D Integrated Circuit (3D IC) ecosystem in collaboration with partners.
This alliance includes companies in electronic design automation (EDA), silicon intellectual property (IP), design center alliances (DCA)/value chain alliances (VCA), memory, outsourced packaging testing (OSAT), and substrate and testing. Members include Ansys, Cadence, Siemens, ARM, Micron, Samsung, SK Hynix, Amkor, ASE, Advantest, and more.
In addition to establishing the alliance, TSMC also introduced the 3Dblox standard during the alliance’s inception. This standard integrates the design ecosystem with validated EDA tools and processes to support 3DFabric technology.
The purpose of this standard is to break the complexity of 3D IC design caused by each EDA supplier using its preferred language. Through the modular 3Dblox standard, key physical stacking and logic connection information in 3D IC design are standardized in a single format, simplifying input and significantly enhancing interoperability among different tools in 3D IC design.
From Intel’s UCIe standard to TSMC’s 3DFabric alliance and 3Dblox standard, it’s evident that in the era of advanced packaging, the key to solidifying the positions and market shares of semiconductor giants lies not only in their individual technological breakthroughs but also in their ability to coordinate and integrate the upstream and downstream industries.
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(Photo credit: TSMC)