In 2022, Intel engaged in negotiations with the Italian government, planning to invest USD 5 billion in constructing a packaging and testing facility. This project would also receive subsidies from the Italian government, expected to cover 40% of the construction costs, along with additional subsidies or incentives. Furthermore, Intel intended to establish a research and design center in France, expected to create a complete semiconductor supply chain in Europe.

However, according to a report from Reuters, Italian Minister of Industry Adolfo Urso has indicated that Intel may delay or abandon its investment plans in Italy and France to fulfill its prior commitments in Germany. Nonetheless, Italy has not completely given up on attracting Intel; Adolfo Urso emphasizes that Italy remains very welcoming if Intel changes its mind.

On the other hand, according to another previous report from Reuters, the US government is expected to announce a significant grant for Intel’s Arizona project soon. This grant will be part of the USD 39 billion direct appropriations and USD 75 billion loans and guarantees under the “Chip Act.”

Among the recipients of subsidies under the “Chip Act,” Intel is expected to receive the largest subsidy to date. According to a previous report from Tom’s Hardware, Intel is anticipated to receive a government subsidy of USD 10 billion, with TSMC and Samsung potentially included in the latest subsidy list as well.

Samsung Electronics is, according to its own expectation, investing USD 17 billion to construct a foundry in Taylor, Texas, while TSMC is investing roughly USD 40 billion to build a foundry in Phoenix, Arizona. However, there are rumors suggesting that due to the U.S. prioritizing domestic companies, the expected subsidy amounts for Intel may differ from those for TSMC and Samsung.

The U.S. government enacted the “Chip Act” in 2022, but subsidies have been modest, with only three American companies currently benefiting, including BAE Systems, GlobalFoundries, and Microchip Technology.

In order to accelerate the development of the IDM 2.0 initiative, Intel made a significant expansion decision in 2021, investing approximately USD 20 billion in the Octillo campus in Arizona, USA. This investment involved the construction of two new fabs and the implementation of EUV production lines to support Intel’s 20A and Intel’s 18A process technologies. The new Fab 52 and Fab 62 are expected to commence operations in 2024.

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(Photo credit: Intel)

According to sources cited by Reuters,  TSMC is reportedly considering plans to establish a production line for its CoWoS technology in Japan. However, TSMC has yet to make any further decisions, and they have declined to comment on the matter.

CoWoS is an advanced packaging technology that stacks chips to enhance computing power, reduce energy consumption, and save space. Currently, TSMC’s CoWoS production capacity is entirely located in Taiwan.

With the booming development of artificial intelligence, global demand for advanced semiconductor packaging has surged, prompting chip suppliers like TSMC, Samsung, and Intel to strengthen their advanced packaging capabilities.

Previously, TSMC’s CEO, C.C. Wei, stated that the company plans to double its CoWoS output by the end of 2024 and further increase it in 2025. With TSMC recently completing the first phase of construction for its Kumamoto fab in Japan and announcing plans for the second phase, which will involve collaboration with Japanese companies SONY Semiconductor Solutions and Toyota Motor Corporation, with a total investment exceeding USD 20 billion and utilizing 6/7-nanometer advanced processes.

However, Joanne Chiao, an analyst at market research firm TrendForce, suggests that if TSMC establishes advanced packaging capacity in Japan, it may face limitations in scale. It remains unclear how much demand there is in Japan for CoWoS packaging, but most of TSMC’s CoWoS customers are currently in the United States.

Additionally, sources cited by Reuters’ report indicate that TSMC’s competitor, Intel, is also considering establishing an advanced packaging research facility in Japan to deepen ties with local chip supply chain companies.

Meanwhile, Samsung, another competitor of TSMC, is setting up advanced packaging research facilities in Yokohama, Japan, with government support. Furthermore, Samsung is in discussions with Japanese and other companies regarding material procurement, preparing to launch its packaging technology similar to that used by SK Hynix.

Regarding the development of the semiconductor industry in Japan, as mentioned in a previous report from TrendForce, Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

However, the looming shortage of semiconductor talent in Japan is a concern. In response, there are generous subsidy programs for talent development. Japan is strategically positioning itself to reclaim its former glory in the world of semiconductors.

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(Photo credit: TSMC)

Samsung, as per a report from the global media outlet wccftech, has decided to enter the next generation of packaging technology by commencing R&D works for the adoption of “Glass Substrate” by 2026.

The report further indicates that Samsung’s preparation to enter the glass substrate industry for advanced packaging is not actually a new endeavor. As several years ago, competitor Intel had already made strides in this area. The commencement of significant production is expected to begin around 2030. In preparation for large-scale production, Intel has already begun establishing production lines in Arizona, investing USD 1 billion.

To address the current market’s capacity gap, Samsung has also initiated plans to commence glass substrate production.

Currently, under the Samsung Group umbrella, Samsung Electronics is in the process of implementing construction plans for production lines and is also conducting research and development on the application of glass substrates in the field of AI chips.

Additionally, Samsung Group is coordinating various departments within its conglomerate, such as Samsung Display, to further ensure the smooth completion of research and development as well as production efforts related to glass substrates.

The report indicates that through the application of advanced packaging technology using glass substrates, there are several advantages over traditional organic substrate packaging techniques, and it can overcome more technical bottlenecks.

For instance, glass substrates can offer higher strength, ensuring greater durability and reliability, as well as higher interconnectivity. Moreover, glass substrates are thinner than typical organic substrates, enabling the linking of more small chips in advanced packaging technology.

Previously, Intel also elaborated on the glass-based substrate packaging technology. According to Intel’s previous press release, glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

However, despite the many application advantages of glass substrates in the current market, the R&D efforts of various companies have encountered difficulties, impacting the market’s application status.

Currently, Samsung Electronics expects to mass-produce glass substrate products in 2026. Whether it can replace traditional organic substrates and advance packaging technology development will be a focal point of market attention.

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(Photo credit: Intel)

Intel has reportedly retained the export licenses that would have prohibited them from selling laptop processor (CPU) chips to the Chinese telecommunications giant Huawei. This signifies that Intel has temporarily preserved its business of providing chips worth hundreds of millions of dollars to Huawei.

According to sources cited by Reuters on March 12th, the US placed Huawei on a trade blacklist in 2019, alleging violations of US sanctions. However, at the end of 2020, the US Department of Commerce granted special licenses to some US suppliers, including Intel, allowing them to sell certain technology products to Huawei.

Still, some sources cited in the report believe that Intel’s license is expected to expire later this year and is unlikely to be renewed.

The sources cited in the same report also stated that Intel’s competitor, AMD, had applied for a similar license to sell comparable chips in early 2021 but did not receive approval from the US Department of Commerce. AMD subsequently protested, claiming that the US government’s differential treatment was unfair.

Regarding this matter, Intel, Huawei, the Commerce Department and the White House declined to comment. AMD did not respond to a request for comment.

As per TrendForce, Intel is forecasted to hold a market share of 68.8% in the CPU market in 2024, while AMD is expected to have a share of 20.2%.

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(Photo credit: iStock)

Recently, IC design company Marvell announced an expansion of its long-term partnership with TSMC to include 2-nanometer technology. They will collaborate on developing the industry’s first 2-nanometer semiconductor production platform optimized for accelerating infrastructure.

Currently, the most advanced production technology in the industry is the 3-nanometer process, manufactured by Samsung Electronics and TSMC. With Intel securing the first ASML lithography machine and updating its latest manufacturing roadmap, and with the increasing collaboration between Rapidus and IBM, the competition for the 2-nanometer advanced process has significantly expanded to include TSMC, Intel, Samsung and  Rapidus.

• Marvell

According to Marvell’s press release, it has stated that Marvell has transitioned from a follower to a leader in integrating advanced node technology into silicon infrastructure.

Marvell first bringing advanced node technology to infrastructure silicon with its 5nm platform, followed by the release of several 5-nanometer designs and the profolio of the first silicon infrastructure product lineup based on TSMC’s 3-nanometer process.

“Tomorrow’s artificial intelligence workloads will require significant and substantial gains in performance, power, area, and transistor density. The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure capable of delivering on the promise of AI,” said Sandeep Bharathi, chief development officer at Marvell.

• TSMC

TSMC commenced mass production of its 3-nanometer process in 2022, with profitability realized starting from the third quarter of 2023. By the fourth quarter of 2023, the 3-nanometer process contributed to 15% of wafer revenue, and its revenue share has been steadily increasing.

According to TrendForce, the foundry market is expected to grow by 7% in 2024, largely attributed to TSMC’s ramp-up of its 3-nanometer process. This has further increased TSMC’s market share.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures. It is anticipated that N2 will commence mass production in 2025, leading the industry in terms of density and energy efficiency.

The N2 backside power delivery solution is slated for release in the latter half of 2025 and is expected to enter mass production in 2026, primarily targeting the High-Performance Computing (HPC) sector.

Furthermore, due to the current high demand for 2-nanometer processes from all AI innovators worldwide surpassing that for 3-nanometer processes, almost all AI innovators are collaborating with TSMC on 2-nanometer process technology. The main applications are primarily focused on high-performance computing (HPC) and smartphones.

Consequently, TSMC has announced plans to expand its production capacity for 2-nanometer processes. Originally, two 2-nanometer fabs were planned for the Kaohsiung facility, but now consideration is being given to constructing a third 2-nanometer fab.

• Samsung

Samsung commenced mass production of its 3-nanometer process in June 2022. According to the latest industry reports, Samsung has developed a “second-generation 3-nanometer” process, renamed as “2-nanometer”, with plans for mass production before the end of this year.

At the 2023 Samsung Foundry Forum, Samsung Electronics unveiled the latest roadmap for its 2-nanometer process. Samsung Electronics President and Head of Foundry Business, Siyoung Choi, disclosed that Samsung will first mass-produce 2-nanometer chips for mobile terminals starting from 2025. Subsequently, in 2026, the technology will be applied to high-performance computing (HPC) products, followed by expansion to automotive chips by 2027.

Unlike TSMC, which opted for Gate-All-Around (GAA) structure at the outset of its 2-nanometer process, Samsung has been utilizing GAA structure since its 3-nanometer process. This suggests that Samsung may have more experience in new structures compared to TSMC, thus giving Samsung an advantage in its 2-nanometer node.

In the past, when Samsung Electronics transitioned from 7-nanometer to 5-nanometer process technology in 2020, the second generation 7-nanometer process technology was renamed as 5-nanometer process technology.

Samsung Electronics’ 7-nanometer process technology became the world’s first to use Extreme Ultraviolet (EUV) lithography in 2019, making it more stable and enabling the company to further shrink transistor sizes. This was also the reason for renaming the second generation 7-nanometer process to 5-nanometer process at that time.

A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.

It is reported that PFN has been collaborating with TSMC since 2016, but this year, it has decided to produce the next generation of AI chips at Samsung’s 2-nanometer node. According to the agreement, Samsung will utilize its latest 2-nanometer chip fab technology to manufacture AI accelerators and other AI chips for PFN.

• Intel

As per Intel’s previously announced plans, the company aims to catch up with and surpass TSMC by 2024 or 2025. At this year’s “Direct Connect” conference hosted by Intel Foundry Services, the company unveiled its latest technological roadmap.

Intel has reported that its primary product, Clearwater Forest, which is under the 18A process, has been completed and is set for production in 2025. Intel’s 18A process is often compared with TSMC’s N2 (2-nanometer) and N3P (3-nanometer) processes in terms of performance, with each company advocating for its own advantages.

Intel CEO Pat Gelsinger emphasizes that both 18A and N2 utilize GAA transistors (RibbonFET), but the 1.8-nanometer node will adopt BSPND, a backside power delivery technology that optimizes power and clock. TSMC, on the other hand, believes that its N3P (3-nanometer) technology will rival Intel’s 18A in power consumption, performance, and area (PPA), while its N2 (2-nanometer) will surpass it in all aspects.

Additionally, Intel’s 20A manufacturing technology is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and backside power delivery network (BSPDN). These aim to achieve higher performance, lower power consumption, and increased transistor density.

Meanwhile, Intel’s 18A production node aims to further refine the innovations of 20A and provide additional PPA improvements from late 2024 to early 2025. Per Intel’s statements regarding its fab processes, its 2-nanometer technology is expected to be the earliest to debut.

Of particular note, Intel announced for the first time at the conference the development of 14A (1.4nm) and its evolutionary version, 14A-E. Intel’s 14A process is the industry’s first node to utilize ASML High-NA EUV lithography tools, making Intel the first company in the industry to acquire cutting-edge High-NA tools. Intel expects to develop 14A by 2027.

• Rapidus

In addition to the aforementioned semiconductor foundries, a Japanese company, Rapidus, is worth noting as well. Established in August 2022, Rapidus was jointly founded by eight Japanese companies including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND Flash giant Kioxia, and Mitsubishi UFJ.

On January 22nd of 2024, Rapidus President Junichi Koike announced during a press conference that construction of the Rapidus 2-nanometer chip fab in Japan is progressing smoothly, and the trial production line is scheduled to commence operations in April 2025 as planned. Additionally, there are plans for the construction of a second and third facility in the future.

In September of last year, Rapidus began construction of Japan’s first logic chip fab, “IIM-1,” in Chitose City, Hokkaido, capable of producing chips below 2 nanometers. It is reported that the fab is expected to be completed by December of this year.

Previously, Rapidus signed a collaboration agreement with IBM to develop technology based on IBM’s 2-nanometer process. IBM had already introduced the world’s first 2-nanometer process chip back in 2021. Similarly, IBM’s 2-nanometer process also utilizes GAA (Gate-All-Around) structure. This partnership provides Rapidus with the technical support necessary for advanced process development.

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(Photo credit: TSMC)