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In June 2023, leading processor manufacturer Intel reached an agreement with the German federal government, announcing the signing of an amended investment memorandum. The plan involves investing over EUR 30 billion to construct two new fabs in Magdeburg. The German federal government has agreed to provide a subsidy of EUR 10 billion, including incentives and subsidies from the European Chips Act and government initiatives.
According to a report by Tom’s Hardware citing sources, Intel has submitted conceptual drawings for a new fab in Germany. The initial plans include two fabs, designated as Fab 29.1 and Fab 29.2, equipped with the world’s most advanced semiconductor tools.
Moreover, Intel reportedly has ample space for up to six additional fabs. The first batch of two fabs is expected to commence operations in the fourth quarter of 2027, with both the Intel 14A (1.4nm) and Intel 10A (1nm) advanced processes believed to be part of the plan.
As per previous reports from TechNews, Intel has not disclosed any details regarding the 10A node, but it promises at least double-digit improvements in power consumption and performance. Intel CEO Pat Gelsinger has previously stated that new processes typically improve critical dimensions by approximately 14% to 15%. Therefore, it is plausible that the 10A and 14A nodes will also experience similar improvements.
As per Intel’s roadmap, Intel 14A is also optimized in 2027, so it seems that 10A falls between 14A and 14A-E.
The report from Tom’s Hardware further indicates that Fab 29.1 and Fab 29.2, the two three-story buildings, occupy approximately 81,000 square meters, with a total length of 530 meters and a width of 153 meters. Each floor has a height ranging from 5.7 to 6.5 meters. Including the roof structure for air conditioning and heating, the building reaches a height of 36.7 meters.
The High-NA EUV exposure machines are installed on the second floor with a height of 6.5 meters, while the upper and lower floors are used for material logistics, providing necessary resources such as water, electricity, and chemicals.
ASML models that the 1st generation of the High-NA-enabled production node will employ between 4 to 9 High-NA EUV exposures and a total of 20 to 30 EUV exposures, encompassing both Low-NA and High-NA.
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(Photo credit: Intel)
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Intel’s foundry has extended its public roadmap, incorporating the Intel 14A process into the advanced process schedule and adding specific nodes. However, recent modifications to the roadmap have moved Intel 14A forward to 2026 and introduced a new process in 2027, namely 1 nanometer (Intel 10A).
According to TechNews citing reports from global media outlets tom’s Hardware and Extremetech, this marks Intel’s first announcement of the commencement of the 1-nanometer process. Although Intel had introduced Intel 10A at its exhibition, the news was restricted until now and has just been disclosed.
Intel 10A is set to enter the production/development (non-mass production) phase in 2027, while Intel 14A (1.4 nanometers) is scheduled for early production in 2026. Additionally, Intel is committed to constructing a fully autonomous AI-driven fab.
Keyvan Esfarjani, Intel’s Executive Vice President and General Manager of Manufacturing and Supply Chain, introduced the latest developments and showcased the technical roadmap. Intel plans to commence development of the 10A node by late 2027 to address gaps in EUV technology.
Assuming that Intel successfully launches its 1.8-nanometer process next year, follows with a 1.4-nanometer process in 2026, and then advances to 1-nanometer in 2027, Extremetech’s report claims that Intel is likely to be ahead of its competitor TSMC. TSMC estimates to begin its 2-nanometer process around 2025 or 2026, followed by a 1.4-nanometer process thereafter.
However, Intel has not disclosed any details regarding the 10A node, but it promises at least double-digit improvements in power consumption and performance. Intel CEO Pat Gelsinger has previously stated that new processes typically improve critical dimensions by approximately 14% to 15%. Therefore, it is plausible that the 10A and 14A nodes will also experience similar improvements.
As per Intel’s roadmap, Intel 14A is also optimized in 2027, so it seems that 10A falls between 14A and 14A-E.
It is worth noting that according to Intel’s presentation notes, the final scale, speed, and process depend on commercial conditions and incentives, implying that funding from the U.S. Chip Act will affect expansion capacity.
Current Technological Developments at Intel
Intel’s 20A integrates two new technologies: backside power (PowerVIA) and GAA transistors (RibbonFET). Additionally, there is a proactive effort to enhance production capacity for advanced packaging technologies such as Foveros, EMIB, SiP (Silicon Photonics), and HBI (Hybrid Bond Interconnect).
Recently, Intel concluded all internal packaging for standard packaging, redirecting focus entirely towards high-end packaging, with standard packaging tasks now handled by OSATs (outsourced assembly and test companies).
While Intel’s 18A production base is located in Arizona, the location for manufacturing the 10A node has not been disclosed.
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Intel, according to South Korea’s media outlet TheElec, is actively promoting its 18A process (equivalent to 1.8 nanometers) to South Korean fabless chip companies.
The report cites industry sources revealing that Intel CEO Pat Gelsinger personally engaged with senior executives of these South Korean fabless IC design companies last year. He briefed them on the latest developments in Intel’s foundry plans.
The same source further indicates that Intel is vigorously marketing the 18A process to South Korean chip startups and pledges various benefits to them.
Last week, Intel unveiled its 14A process, equivalent to a 1.4-nanometer process, and announced that chips utilizing this process will enter mass production in 2027. Intel has also announced that it has secured USD 15 billion in orders during its event Intel Foundry Direct Connect at San Jose.
Intel continues to emphasize its goal of becoming the second-largest foundry by 2030, aiming to surpass current foundry runner-up Samsung Electronics and trailing behind market leader TSMC.
As for the mass production of the 18A process, Intel has indicated that it is scheduled to commence by the end of this year. This signifies that Intel’s process technology will surpass both Samsung and TSMC, as the latter two are currently preparing to launch 2-nanometer processes.
Samsung is planning to utilize the gate-all-around (GAA) transistor architecture, initially developed for the 3-nanometer process, for its upcoming 2-nanometer process. On the other hand, TSMC and Intel have opted to employ the fin field-effect transistor (FinFET) structure for their 3-nanometer chips.
Currently, these three major players are actively vying for customers. A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.
Per the report, while this Japanese company initially planned to use TSMC’s process for producing their Gen 2 AI chips, they will now transition to Samsung’s 2-nanometer process.
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(Photo credit: Intel)
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U.S. Commerce Secretary Gina Raimondo previously mentioned during an online Intel foundry event that the U.S. must continue investing to regain global leadership and requires “Chip Act 2.”
According to a report from TechNews citing from global media Tom’s Hardware, the U.S. Department of Commerce plans to announce additional subsidies for the semiconductor bill as soon as this week.
Raimondo is scheduled to attend the “Revitalizing American Innovation” conference hosted by the Center for Strategic and International Studies (CSIS) in Washington on February 26th and will unveil the latest subsidies under the “Chip Act.”
In this regard, Intel is expected to receive a government subsidy of USD 10 billion, while TSMC and Samsung may also be included in the latest subsidy list. Samsung Electronics is, according to its own expectation, investing USD 17 billion to construct a foundry in Taylor, Texas, while TSMC is investing roughly USD 40 billion to build a foundry in Phoenix, Arizona. However, it’s rumored that due to the U.S. prioritizing domestic companies, the expected subsidy amounts may differ from those of Intel.
The U.S. government enacted the “Chip Act” in 2022, but subsidies have been modest, with only three American companies currently benefiting, including BAE Systems, GlobalFoundries, and Microchip Technology.
Due to Intel’s investment of USD 43.5 billion in the United States since 2021, constructing new semiconductor plants, sources cited by the report believe that the likelihood of Intel receiving USD 10 billion (equivalent to 23% of the investment amount) is quite high.
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(Photo credit: TSMC)
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As Intel’s January announced the collaboration with UMC on the 12-nanometer process platform, UMC’s Co-General Manager, Jason Wang, led a team to support Intel’s IFS event.
Cited by Commercial Times in its report, Wang emphasized that UMC’s existing customers would have more production location options and benefit from the platform strategy. UMC will seamlessly transition from the 28/22-nanometer to the critical 12-nanometer.
Followed by joint interviews to share insights into the future strategies of both parties, Wang stated that in the face of rapid changes and challenges in the external environment, industries need to strengthen their cooperative relationships and seize opportunities for collaboration.
Intel and UMC announced their collaboration at the end of January, focusing on the development of a shared platform for the 12-nanometer process. In the future, UMC will be able to expand its orders for the front-end of the 12-nanometer process, while Intel will secure orders for the 12-nanometer wafer manufacturing.
Jason Wang emphasized that UMC has a comprehensive solution for the 28/22-nanometer, with demand trending towards stability. However, due to past limitations in resource allocation , UMC has paused at the 14/16-nanometer. Advancing to more advanced processes is just a matter of timing.
Wang further stated that both parties will focus on creating customer value, breaking frameworks, and innovating in cooperation. The two companies complement each other’s strengths, accelerating the timeline for technological development and expanding their global footprint.
Wang revealed that Intel has already included UMC’s 12-nanometer process in its product roadmap and has begun deep collaboration. UMC has deployed personnel to oversee this, with Intel leveraging UMC’s know-how in management.
Additionally, the collaboration involves revenue sharing rather than the rumored licensing fees. They anticipate completing the Process Design Kit (PDK) by next year and achieving mass production by the end of 2026.
Overall, TrendForce views this alliance as a significant step. UMC brings its plentiful experience in mature processes, while Intel contributes its advanced technological prowess.
This partnership is not just about mutual benefits at the 10nm process level; it’s a watchpoint for potentially deeper and more extensive collaboration in their respective fields of expertise. In the dynamic world of semiconductor manufacturing, this Intel-UMC alliance is a fascinating development to keep an eye on.
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(Photo credit: Intel)