According to a report from Taiwan’s Economic Daily, TSMC’s 3-nanometer technology has attracted another heavyweight client. Following Apple and MediaTek, it is rumored that Qualcomm will also commission TSMC to produce its next-generation 5G flagship chip using the 3-nanometer process. The chip is expected to be unveiled in late October, making Qualcomm the third client for TSMC’s 3-nanometer technology.

In response to these rumors, Qualcomm has not provided any comments, while TSMC has chosen to remain silent. Industry experts speculate that TSMC’s 3-nanometer technology will likely attract additional orders from major players such as NVIDIA and AMD in the future. With various leading-edge fabs continuously seeking TSMC’s services, it appears that TSMC’s 3-nanometer technology remains the top choice for international giants.

Last year, Qualcomm unveiled its annual 5G flagship chip, the “Snapdragon 8 Gen 2,” manufactured using TSMC’s 4-nanometer process. The previous-generation Snapdragon “8 Gen 1” was produced using Samsung’s 4-nanometer process, but it encountered issues related to heat dissipation. Consequently, Qualcomm released an upgraded version, the “Snapdragon 8+ Gen 1,” using TSMC’s 4-nanometer process.

Qualcomm has traditionally adopted a multi-supplier strategy for semiconductor manufacturing. It is rumored in the industry that Qualcomm has privately informed its smartphone brand customers about the upcoming next-generation 5G flagship chip, the “Snapdragon 8 Gen 3,” expected to be announced in late October. This chip will be available in two process versions: TSMC’s 4-nanometer (N4P) and 3-nanometer (N3E).

(Photo credit: TSMC)

According to Taiwan’s Money DJ, the AI wave is showing no signs of slowing down. Led by NVIDIA, major players including AMD, Intel, and international chip giants are aggressively entering the AI arena, driving increasing demand for advanced packaging and advanced processes. Industry reports suggest that TSMC is reallocating several thousand personnel from its Hsinchu 12B plant to support its Longtan and Tainan 18B facilities in a bid to address the current urgent demands.

TSMC typically follows a process of initial research and development (R&D) stages for advancing its processes before handing them over to the mini-line teams and then proceeding to full-scale production. As a result, the 2nm process is slated for trial production in the second quarter of 2024, leaving a gap of approximately six months. It is rumored that TSMC is mobilizing staff from its Hsinchu 12B plant to provide support for the CoWoS-focused Longtan facility and the Tainan 18B plant, which is responsible for mass-producing the 3nm process, to address the immediate needs.

Equipment suppliers estimate that TSMC’s CoWoS production capacity is set to reach 12,000 to 14,000 wafers per month by the end of this year, with a projected doubling of production by 2024. By the end of that year, it is expected to reach at least 26,000 wafers per month, potentially even surpassing 30,000 wafers. Meanwhile, for the 3nm family, in addition to Apple and MediaTek, AMD, NVIDIA, Qualcomm, and even Intel are confirmed to adopt the N3 family of processes.

(Photo credit: TSMC)

According to Taiwan’s Business Next, as Moore’s Law gradually reaches its limits, semiconductor manufacturers are transitioning from 2D to 3D chip stacking and packaging to increase transistor counts for improved performance. The final step, “packaging,” has become crucial. In line with this trend, Intel has announced the industry’s first glass-based substrate for advanced packaging, breaking traditional constraints, with mass production expected between 2026 and 2030.

Intel’s glass-based substrate packaging technology has been in development for a decade and was unveiled at the 2023 Innovation Day in Silicon Valley, USA. Intel aims to achieve the goal of accommodating 1 trillion transistors within a single package by 2030 using advanced glass-based packaging.

The rise of the AI wave has driven the demand for accelerated computing, increasing the requirements for chip density. Intel argues that current substrate materials consume more power and are more prone to expansion and warpage compared to glass, which better aligns with future needs. Industry analysts have noted that TSMC also has similar solutions.

According to Intel, Glass substrates can tolerate higher temperatures, offer 50% less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable ultra-large form-factor packages with very high assembly yields.

Glass substrates’ tolerance to higher temperatures also offers chip architects flexibility on how to set the design rules for power delivery and signal routing because it gives them the ability to seamlessly integrate optical interconnects, as well as embed inductors and capacitors into the glass at higher temperature processing.

According to a report from China’s Changjiang Securities released in May, the application of glass substrates in advanced packaging has been validated, and glass manufacturer Corning has introduced related products.

On the other hand, in a report by China’s Changjiang Securities released in May, the application of glass substrates in advanced packaging has been validated, with glass manufacturer Corning introducing related products.

(Photo credit: Intel)

Report to Liberty Times Net, In a joint statement on the comprehensive strategic partnership between the United States and Vietnam, the two countries highlighted Vietnam’s significant potential to become a key player in the semiconductor industry. The United States expressed its support for the rapid development of Vietnam’s semiconductor ecosystem. To foster the development of human resources in the semiconductor industry, the United States will provide a $2 million seed fund, with future investments coming from the Vietnamese government and the private sector. These initiatives are seen as a significant step forward for Vietnam in its journey to join the global semiconductor industry.

U.S. census data showed semiconductor imports from Vietnam surged by 75% to $562.5 million in August compared to the same period last year, capturing approximately 11.6% of the market share. However, experts point out that considering the entire supply chain, Vietnam’s contribution remains relatively small.

Semiconductor manufacturing involves three fundamental stages: design, fabrication, and packaging. Since Intel’s Ho Chi Minh City factory is its primary production facility, Vietnam is primarily involved in the final packaging stage of semiconductor production, which represents the lowest value-added segment of the supply chain. According to data from the Semiconductor Industry Association (SIA), packaging accounts for only 6% of the chip’s value. Additionally, Korean semiconductor design companies are following Samsung’s lead by establishing factories in Vietnam, including CoAsia in Hanoi and Amkor in Bac Ninh province.

Shortage of Engineers in Vietnam Poses a Major Challenge

A shortage of packaging and design engineers poses a significant challenge for Vietnam. The country lacks the capacity for domestic semiconductor manufacturing. Currently, Vietnam has over 5,500 semiconductor design engineers, while Intel’s Ho Chi Minh City factory has shipped over 3 billion chips to date. The supply chain ecosystem of American giants is gradually taking shape in Vietnam. However, with just over 5,000 engineers, Vietnam remains a distant bridge to this multi-billion-dollar industry.

Vietnam faces two choices for industry growth: expanding its manufacturing sector or enhancing skills and value in the design and packaging phases. Experts suggest that Vietnam has chosen the latter. However, the shortage of personnel poses a barrier to Vietnam’s ambitions to increase the value of its semiconductor supply chain.

According to estimates, the semiconductor industry needs to cultivate 10,000 engineers annually, but Vietnam’s current rate is less than 20%. In fact, according to a report by the Vietnam Microchip Association, the number of engineers only increases by about 500 people each year. Currently, most of Vietnam’s semiconductor engineers work for foreign companies.

(Source: https://ec.ltn.com.tw/article/breakingnews/4432014)

In recent years, with the rise of AI and 5G technologies leading to increasing computational demands, Silicon Photonics technology has once again become a focal point of discussion in the semiconductor industry.

TrendForce Perspective:

• Rewriting Semiconductor Development Rules with Silicon Photonics 

Since the development of the semiconductor industry, the industry’s trajectory has largely followed the development predicted by Gordon Moore – roughly doubling the number of transistors that can be accommodated on an integrated circuit approximately every two years. However, as chip sizes continue to shrink, chip architecture design is gradually being challenged. Semiconductor manufacturers, including TSMC, Samsung, and Intel, are striving to break through Moore’s Law as their goal. Others have publicly announced their focus on mature processes (the industry divides at 7nm, with 7nm and below considered advanced processes) and optimization of existing technologies.

However, even as manufacturers push the boundaries of Moore’s Law, leading to increased transistor density per unit area, signal loss issues inevitably arise during signal transmission since chips rely on electricity to transmit signals. Despite the increased transistor count, power consumption problems persist. Silicon Photonics technology, which replaces electrical signals with optical signals for high-speed data transmission, successfully overcomes this challenge, achieving higher bandwidth and faster data processing. With this approach, chips do not need to cram more transistors per unit area or pursue smaller nanometers and nodes. Instead, they can achieve higher integration and performance on existing processes, further advancing technology.

• Optimistic about Silicon Photonics Technology, but Breakthroughs Will Take Time

Currently, Silicon Photonics technology still faces various challenges, including alignment and coupling, thermal management, modulation and detection, expansion and integration, among others. Significant breakthroughs are unlikely in the short term, and major global manufacturers are still in the early development stages. In Taiwan, recent reports suggest that TSMC is actively venturing into Silicon Photonics technology. While TSMC has not officially confirmed this news, during the Silicon Photonics International Forum, a senior vice president from TSMC clearly stated, “If a good Silicon Photonics integration system can be provided, it can address the key issues of energy efficiency and AI computing power. This could be a Paradigm Shift, and we might be at the beginning of a new era.”

This suggests that TSMC is optimistic about the development of Silicon Photonics technology. Although Taiwanese companies have not formally announced their entry into the Silicon Photonics field, it is expected that with the explosive growth in demand for data transmission, storage, and computing driven by AI technology, Silicon Photonics will undoubtedly be a critical technology for future semiconductor development.