NVIDIA’s AI chip supply faces constraints, with insufficient CoWoS advanced packaging production capacity at TSMC potentially being the main issue. According to Economic Daily News, NVIDIA is also providing advanced packaging services to Intel, with a monthly capacity of about 5,000 units. It is expected to join NVIDIA’s advanced packaging supply chain as early as the second quarter in 2024, grabbing a share of TSMC’s related orders.

Industry sources cited by the Economic Daily News believe that Intel’s participation will help alleviate the tight supply of AI chips.

TSMC declined to comment on the rumors on January 30th. As per industry sources cited by Economic Daily News, Intel’s entry into NVIDIA’s advanced packaging supply chain is expected to lead to a significant increase of nearly ten percent in total production capacity.

As per industry analysis cited in the report, even with Intel joining to provide advanced packaging capacity for NVIDIA, TSMC remains NVIDIA’s primary supplier for advanced packaging. When considering the expanded production capacity of TSMC and other related assembly and testing partners, it is estimated that they will supply approximately 90% of advanced packaging capacity for NVIDIA.

Supply chain sources cited by the report further indicate that TSMC is ramping up its advanced packaging production capacity. Production capacity is estimated to increase to nearly 50,000 units in the first quarter of this year, representing a 25% increase from the estimated nearly 40,000 units in December last year.

While Intel may potentially provide NVIDIA with nearly 5,000 units of advanced packaging capacity, this accounts for about 10% of the total. However, Intel is reportedly not involved in NVIDIA’s AI chip foundry orders.

Intel has advanced packaging capacity in Oregon and New Mexico in the United States and is actively expanding its advanced packaging capabilities in its new facility in Penang. It is noteworthy that Intel previously stated its intention to offer customers the option to only use its advanced packaging solutions, expected to provide customers with greater production flexibility.

Industry sources also indicate that the previous shortage of AI chips stemmed from three main factors: insufficient capacity in advanced packaging, tight supply of high-bandwidth memory (HBM3), and some cloud service providers placing duplicate orders. However, these bottlenecks have gradually been resolved, and the improvement rate is better than expected.

(Photo credit: Intel)

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Japanese telecommunications operator NTT is reportedly collaborating with American chipmaker Intel and other semiconductor manufacturers to research large-scale production of next-generation semiconductor technology, which involves significantly reducing power consumption using optical technology.

According to a report from Nikkei, SK Hynix is also set to participate in this initiative, expected to counter China through collaborative research and development strategies.

Meanwhile, the Japanese government will provide approximately JPY 45 billion in support. As cited by Nikkei quoting Japan’s Ministry of Economy, Trade, and Industry, Japan can lead the world in this technology as part of its strategy to revitalize the national semiconductor industry.

These companies are reportedly aiming to develop equipment manufacturing technology that integrates light with semiconductors and memory technology capable of storing data at Terabit-class speeds by the fiscal year 2027. Intel will provide technical development suggestions, aiming to reduce power consumption by 30-40% compared to conventional products.

As semiconductor scaling reaches physical limits, as per a report from TechNews, the industry is turning towards light. When combined with semiconductors, known as silicon photonics, it is expected to significantly reduce energy consumption. This technology is also seen as potentially game-changing for the semiconductor industry.

Signals received through optical communication is converted into electrical signals by specialized equipment, which are then transmitted to data center servers. Semiconductors within the servers then exchange electrical signals to process computations and memory. With the proliferation of AI and the need to process massive amounts of data, the demand for optical technology is anticipated to increase.

The integration of silicon photonics still presents numerous challenges, primarily concerning interface communication protocols. Consequently, synchronization in communication among semiconductor manufacturers is essential for the realization of silicon photonics technology.

Therefore, NTT aims to coordinate necessary technologies through collaboration with Intel and SK Hynix.

NTT holds a global leadership position in integrating optical and electronic technologies, having successfully pioneered the foundational technology of using light for transistor circuits. This achievement was published in the British scientific journal “Nature Photonics” in 2019, leading to the introduction of the IOWN (Innovative Optical and Wireless Network) fully optical network based on this technology.

(Photo credit: Intel)

Intel announced on the evening of January 25th that it will collaborate with UMC to develop 12-nanometer process platform technology. The production will utilize Intel’s wafer fab capacity in the United States, and both parties will share the cash generated from the collaboration. The production is expected to commence in 2027.

This marks Intel’s first collaboration with a Taiwanese foundry in process development. Intel is actively venturing into the foundry business, and this collaboration with UMC not only marks a new milestone in the Taiwan-US semiconductor foundry industry but also initiates a new competitive relationship in the global foundry industry.

Intel and UMC have not disclosed the expected investment amount for their collaboration. UMC stated that the investment amount cannot be disclosed as the collaborative technology will not enter production until 2027, at which point it will begin contributing to revenue.

Therefore, the investment will be shared by both parties. Regarding whether they will advance towards more advanced processes, UMC stated that they do not respond to distant matters and primarily focus on financial indicators that the company can afford.

Intel noted that the collaboration with UMC to develop the 12-nanometer process platform is primarily aimed at addressing the high growth in markets such as mobile, communication infrastructure, and networking.

This long-term collaboration combines Intel’s large-scale manufacturing capacity in the United States with UMC’s extensive experience in mature processes in foundry, expanding the process portfolio while providing a better regionally diversified and resilient supply chain to assist global customers in making better procurement decisions.

The new process node, according to Intel, will be developed and manufactured in Fabs 12, 22 and 32 at Intel’s Ocotillo Technology Fabrication site in Arizona.

“Taiwan has been a critical part of the Asian and global semiconductor and broader technology ecosystem for decades, and Intel is committed to collaborating with innovative companies in Taiwan, such as UMC, to help better serve global customers,” said Stuart Pann, Intel senior vice president and general manager of Intel Foundry Services (IFS).

He further stated that, “Intel’s strategic collaboration with UMC further demonstrates our commitment to delivering technology and manufacturing innovation across the global semiconductor supply chain and is another important step toward our goal of becoming the world’s second-largest foundry by 2030.”

Jason Wang, UMC co-president, said that UMC’s collaboration with Intel on a U.S.-manufactured 12 nm process with FinFET capabilities in the United States is a crucial aspect of the company’s pursuit of cost-effective capacity expansion and technological node advancement.

UMC anticipates that this collaboration will assist customers in smoothly migrating to this critical node while benefiting from the resilience of the expanded capacity in the North American market.

UMC looks forward to strategic collaboration with Intel, leveraging the complementary advantages of both parties to expand potential markets and significantly accelerate technology development timelines.

TrendForce believes that this partnership, which leverages UMC’s diversifed technological services and Intel’s existing factory facilities for joint operation, not only aids Intel in transitioning from an IDM to a foundry business model, it also allows UMC to agilely leverage FinFET capacity without the pressure of heavy capital investments.

TrendForce forecasts that this collaboration slashes average investment by a staggering 80%, compared to the cost of new equipment. This calculation includes only the expenses related to the relocation of equipment, secondary piping costs for factory services, and other minor associated expenses for ancillary equipment.

However, the journey is not without its challenges. UMC’s 14nm process, in development since 2017, is yet to hit mass production, and its 12nm process is still in the R&D phase, with mass production eyed for late 2026. This collaboration’s mass production timeline is tentatively set for 2027, with the FinFET architecture’s stability under careful watch.

Overall, TrendForce views this alliance as a significant step. UMC brings its plentiful experience in mature processes, while Intel contributes its advanced technological prowess.

This partnership is not just about mutual benefits in the 10nm process level; it’s a watchpoint for potentially deeper and more extensive collaboration in their respective fields of expertise. In the dynamic world of semiconductor manufacturing, this Intel-UMC alliance is a fascinating development to keep an eye on.

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(Photo credit: Intel)

According to the report from TechNews, Intel CEO Pat Gelsinger, speaking at the World Economic Forum, stated that export sanctions from the United States, Japan, and the Netherlands are temporarily limiting China’s development in semiconductor processes below 7 nanometers.

Despite China’s ongoing efforts to advance its semiconductor industry and design more sophisticated chip manufacturing tools, it still lags behind the global semiconductor industry by approximately ten years, and Gelsinger believes this gap will persist.

Gelsinger suggests that to some extent, the policies of the United States, Japan, and the Netherlands set a threshold of 10 to 7 nanometers for China’s semiconductor industry. Currently, SMIC has 7-nanometer technology, lagging approximately five and a half years behind TSMC and Samsung. Shanghai Huali Microelectronics (HLMC) began trial production based on 14-nanometer FinFET process in 2020, trailing TSMC by nine to ten years.

Both SMIC and HLMC utilize manufacturing equipment and materials from the Netherlands, Japan, South Korea, Taiwan, and the United States. However, due to the unavailability of these raw materials, Chinese companies have had to develop their own wafer fab equipment and find methods for purifying gases, resists, and other chemicals used in advanced chip manufacturing.

Gelsinger estimates that China’s semiconductor industry lags behind the global standard by about ten years and, although it will continue to develop, he foresees this gap persisting for the next decade. Given the highly interconnected nature of the semiconductor industry, encompassing companies like Zeiss, ASML, Japanese chemical suppliers, and Intel for mask manufacturing, he believes that this cumulative difference amounts to a ten-year gap and will continue to do so under export policies.

If China cannot acquire advanced chip equipment and technology, Chinese semiconductor companies might attempt to narrow the gap with the global semiconductor industry through reverse engineering and replication. While not a sustainable approach, it may be the only choice available.

Regarding advanced processes, Gelsinger also mentioned that Intel is actively developing technologies below 2 nanometers and is looking beyond to 1.5 nanometers, stating, “We are racing to go below 2nm and then 1.5nm, and you know we see no end to that in sight.”

(Image: Intel)

TSMC announced during its briefing on the 18th that, due to robust demand in the 2-nanometer market, it plans to add another fab to the initially planned two fabs in Kaohsiung.

The company intends to use the 2-nanometer process for all three fabs in Kaohsiung, in addition to the originally planned 2-nanometer fab in Hsinchu’s Baoshan. Furthermore, the land recently acquired in Hsinchu Science Park will also be designated for a 2-nanometer fab. This reflects the strong preference for the 2-nanometer process among customers and underscores TSMC’s confidence in its in-house 2-nanometer process technology.

According to a report by TechNews following the briefing on the 18th, TSMC’s CFO Wendell Huang, stated in a media gathering that the strong demand in the high-performance computing and smartphone markets prompted the decision to increase the number of fabs in Kaohsiung from the originally planned two to three. Once the three 2-nanometer fabs are in full production, Kaohsiung will become a crucial manufacturing hub for TSMC’s 2-nanometer process.

In addition, with the recent approval from the Ministry of the Interior’s Urban Planning Commission, the land in Hsinchu Science Park designated for TSMC’s use, expected to be available in June 2024, is also being planned for a 2-nanometer fab.

Recent market reports suggest that TSMC, the leading semiconductor foundry, is set to proceed as scheduled with its plan to adopt the GAA (Gate-All-Around) architecture from the 2-nanometer process onward.

The P1 wafer fab in Baoshan, located in the Hsinchu Science Park, is anticipated to begin equipment installation as early as April 2024, while the Kaohsiung fab is projected to commence production using the GAA architecture for the 2-nanometer process technology in 2025.

Furthermore, in response to Intel securing the first High-NA EUV exposure equipment from ASML for its 18A advanced process, TSMC has indicated that it is also planning for High-NA EUV exposure equipment. However, the current timeline anticipates engineering verification of the High-NA EUV exposure equipment in 2024, with gradual integration into the manufacturing process set to follow.

(Image: TSMC)