The global foundry advanced process battle is reigniting, as reported by the Commercial Times. TSMC’s 2-nanometer process at the Baoshan P1 wafer fab in Hsinchu is set to commence equipment installation as early as April, incorporating a new Gate-All-Around (GAA) transistor architecture and aiming for mass production in 2025.

Additionally, expansion plans for Baoshan P2 and the Kaohsiung fab are projected to join in 2025, with evaluations underway for Phase 2 in the Central Taiwan Science Park. The competition with Samsung and Intel in the most advanced process is intensifying.

Semiconductor industry sources note the ongoing progress in global foundry advanced processes, with Samsung entering GAA architecture early at 3 nanometers, though facing yield challenges, while Intel anticipates mass production of its RibbonFET architecture at 20A this year.

In response to fierce competition, TSMC must accelerate its pace. The ‘Gate-All-Around’ (GAA) technology is a critical factor determining whether chip processing power will double within 1.5 to 2 years.

As per the report, Samsung’s attempt to lead in the 3-nanometer chip segment, transitioning from traditional FinFET, has faced stability issues in yield, hampering customer adoption, and giving TSMC confidence in its 3-nanometer progress. This also highlights the increased complexity in transitioning from 2D to 3D chip designs with GAA transistor architecture.

Furthermore, Intel is intensifying its efforts to catch up, planning to launch Intel 20A in the first half of the year and Intel 18A in the second half. However, it is speculated that Intel 20A will be exclusively used for Intel’s own products, maintaining a close collaboration with TSMC.

TSMC, adopting a cautious approach, benefits from a more advantageous cost structure by minimizing changes in production tools within the same process technology and manufacturing flow. For customers, altering designs during advanced process development incurs significant time and economic costs.

Supply chain sources reveal that TSMC finalized various parameters for its 2-nanometer process at the end of last year, confirming specialty gases and equipment. Contracts are gradually being signed, with equipment installation at the Baoshan P1 fab scheduled to commence in April. Equipment industry sources suggest that TSMC’s process advancement is progressing rapidly as expected, speculating that there will be updates on the Baoshan P2 fab later this year.

(Image: TSMC)

On January 9th, Intel unveiled its latest automotive AI chips, entering into direct competition with rivals NVIDIA and Qualcomm in the automotive chip market. In a bid to strengthen its position, Intel also announced the acquisition of automotive chip company Silicon Mobility.

Reportedly, Intel stated that Silicon Mobility, a French startup, specializes in designing System-on-a-Chip (SoC) technology for controlling electric vehicle motors and in-car charging systems, along with software. The acquisition amount was not disclosed by Intel.

As per Reuter citing from Intel’s automotive business chief Jack Weast, he has indicated that, intel’s new automotive system on a chip products will adapt the company’s recently launched AI PC technology for the durability and performance requirements of vehicles.

Weast further clarified, “Intel will not require automakers to use advanced driving chips designed by its former Mobileye unit, he said. Instead, automakers can have Intel incorporate their own chiplets to enable specific functions into the Intel system at a lower cost.”

Intel’s chips designed for infotainment systems are already integrated into 50 million vehicles. As the automotive chip market continues to expand, the demands on chips are increasing, covering technologies such as autonomous driving, upgradable in-car system software, and complex dashboard displays amid strong competition from NVIDIA and Qualcomm.

Weast has addressed ahead of the CES technology show in Las Vegas that Chinese automaker Zeekr will be the first automaker to use Intel’s AI system on a chip to create “an enhanced living room experience” in vehicles, including AI voice assistants and video conferencing. Zeekr, an electric vehicle brand under the Geely Holding Group, is a customer of both Intel and NVIDIA.

Intel will try to separate itself from rivals by offering chips that automakers can use across their product lines, from lowest-priced to premium vehicles, Weast said.

According to Reuter, Weast addressed reporters in a conference call before the announcement at the CES technology show in Las Vegas, stating, “Intel has done a pretty terrible job communicating our success in automotive, We are going to change that.”

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(Photo credit: Intel)

Intel recently announced that it has acquired the market’s first ASML Extreme Ultraviolet (EUV) exposure equipment with a 0.55 Numerical Aperture (High-NA), aiming to advance its chip manufacturing technology in the coming years. In contrast, TSMC appears to be taking a more cautious approach, currently showing no urgency to join the race for this next-generation exposure technology.

The High-NA EUV exposure equipment obtained by Intel will initially be used for learning and mastering the technology, with plans to implement it in the Intel 18A process node in the next two to three years. 

Industry sources suggest that unlike Intel’s plan to introduce High-NA EUV and GAA transistors simultaneously in the Intel 18A process technology, it is anticipated that TSMC may not adopt this technology until the 1.4nm (A14) node, possibly in 2030 or later.

According to a report from IThome, in fact, Intel’s proactive development roadmap includes implementing the RibbonFET gate-all-around (GAA) transistor architecture and PowerVia backside power delivery technology starting from the Intel 20A process.

Subsequently, further optimizations are expected in the Intel 18A process, followed by the adoption of High-NA EUV exposure equipment in subsequent process nodes after Intel 18A. These advancements is anticipated to achieve lower power consumption, higher performance, and smaller chip sizes.

In addition, Intel plans to introduce pattern shaping starting from the 20A process, followed by the adoption of High-NA EUV after the 18A node. This approach is expected to reduce the complexity of the manufacturing process and avoid the use of EUV double patterning.

However, some professionals in the industry have stated that, at least in the initial stages, the cost of High-NA EUV may be higher than that of Low-NA EUV. Furthermore, High-NA EUV lithography equipment present a series of specific challenges too, including a halving of the exposure area.

These are two of the reasons why TSMC is currently adopting a cautious approach. TSMC tends to favor the use of cost-effective mature technologies to ensure product competitiveness.

In fact, If we look back at the development of EUV technology, TSMC began using EUV exposure equipment in chip production as early as 2019, a few months later than Samsung but several years ahead of Intel. Currently, Intel is expected to take the lead in the High-NA EUV field ahead of Samsung and TSMC to gain a certain technological and strategic advantage, increasing its appeal to customers.

Therefore, whether TSMC can maintain its leading position in process technology, especially if it adopts High-NA EUV exposure machines later than competitors, remains subject to ongoing observation.

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(Photo credit: ASML)

Examining the dynamics of advanced semiconductor manufacturing, from research and development to the competition for cutting-edge equipment and securing orders, major players such as TSMC, Samsung, and Intel are constantly in action. Simultaneously, newcomer Rapidus is making a strong entrance. The competition for advanced processes is set to intensify in 2024.

Amidst the global chipmakers’ race to develop 2-nanometer processes, TSMC has once again emerged victorious by securing Apple’s order. The upcoming iPhone 17 Pro, expected to be released in 2025, reportedly will feature TSMC’s 2-nanometer chip. Samsung is also gearing up to launch a 2nm prototype in 2024, reportedly offering discounted prices with the aim of attracting customers such as NVIDIA.

However, industry insiders reveal that TSMC is on the verge of finalizing its clients for future 3nm and 2nm technologies, apart from Apple, AMD, NVIDIA, Broadcom, MediaTek, and Qualcomm are among the clients for TSMC’s 3nm and 2nm processes. The changes in the customer portfolio of TSMC, Samsung, and Intel in 2024 are bound to be the focal point throughout the year.

(Image: TSMC)

Intel CEO Pat Gelsinger has discussed around Intel’s process status, comparisons with TSMC in a recent interview. According to Barron’s report, Gelsinger mentioned in the interview that Intel’s 18A process and TSMC’s N2 process seem comparable, with no significant advantage for either of them.

However, Gelsinger claimed that, ‘But the backside power delivery, everybody says Intel, score.’ He further stated, ‘it gives better area efficiency for silicon, which means lower cost. It gives better power delivery, which means higher performance.’

Gelsinger mentioned that good transistor and great power delivery make 18A a little bit ahead of N2. Besides, TSMC has given a very high-cost envelope, where Intel can fit underneath to be margin accretive.

In fact, not only TSMC and Intel, but also including Samsung, the three semiconductor manufacturing giants are actively positioning themselves in the increasingly competitive field of advanced process technology.

At the recent IEEE International Electron Devices Meeting (IEDM), Intel, TSMC, and Samsung each showcased their CFET (Complementary FET) transistor solutions. The stacked CFET transistor architecture involves stacking two types of transistor -nFETs and pFETs- together, aiming to replace Gate-All-Around (GAA) and become the next-generation transistor design for doubling density.

As reported by IEEE Spectrum, Intel was the first foundry to showcase the CFET solution, publicly unveiling an early version back in 2020. During the conference, Intel introduced one of the simplest circuits manufactured with CFET, focusing on improvements for an inverter.

The CMOS inverter sends the same input voltage to the gates of two-transistor stacked together, generating an output that is logically opposite to the input, and the inverter is completed on a single fin.

Intel also improved the CFET stack’s electrical characteristics by increasing the number of nanosheets per device from two to three, decreasing the separation between the two devices from 50 nm to 30 nm.

According to the current progress, experts, as indicated by IEEE Spectrum, anticipate that the commercialization of CFET technology on a large scale will likely take another 7 to 10 years from now. Before reaching that stage, there are still many preparatory tasks that need to be completed.

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(Photo credit: Intel)