With the increasing demand for massive computing in fields such as AI, communication, and autonomous vehicles, the evolution of integrated circuits (ICs) has reached a physical limit under the premise of Moore’s Law. How can this limit be surpassed? The answer lies in the realm of optics. Currently, many domestic and international companies are actively embracing “Silicon Photonics” technology. When electronics meet photons, it not only addresses the signal transmission loss issue but is also considered a key technology that could usher in a new era, potentially revolutionizing the future world.

Integrated circuits (ICs) cram millions of transistors onto a single chip, performing various complex calculations. Silicon Photonics, on the other hand, represents integrated “light” paths, where light-conductive pathways are consolidated. In simple terms, it is a technology that converts “electronic signals” into “optical signals” on a silicon platform, facilitating the transmission of both electrical and optical signals.

As technology rapidly advances and computer processing speeds increase, communication between chips has become a critical factor in computing performance. For instance, when ChatGPT was first launched, there were issues with lag and interruptions during the question and answer process, which were related to data transmission problems. Therefore, as AI technology continues to evolve, maintaining computational speed is a crucial aspect of embracing the AI era.

Silicon Photonics has the potential to enhance the speed of optoelectronic transmission, addressing the signal loss and heat issues associated with copper wiring in current computer components. Consequently, semiconductor giants such as TSMC and Intel have already invested in related research and development efforts. In this context, we interviewed Dr. Fang Yen Hsiang, director of the Opto-Electronics Micro Device & System Application Division and Electronic and Optoelectronic System Research Laboratories at the Industrial Technology Research Institute (ITRI), to gain insights into this critical technology.

What Is the Relationship Between Silicon Photonics and Optical Transceivers?

An optical transceiver module comprises various components, including optical receivers, amplifiers, modulators, and more. In the past, these components were individually scattered on a PCB (printed circuit board). However, to reduce power consumption, increase data transmission speed, and minimize transmission loss and signal delay, these components have been integrated into a single silicon chip. Fang emphasizes that this integration is the core of Silicon Photonics.

Integrated Circuits’ Next Step: The Three Stages of Silicon Photonics

• Silicon Photonics Stage 1: Upgrading from Traditional Pluggable Modules

Silicon Photonics has been quietly developing for over 20 years. The traditional Silicon Photonics pluggable optical transceiver modules look very much like USB interfaces and connect to two optical fibers—one for incoming and one for outgoing light. However, the electrical transmission path in pluggable modules had a long distance before reaching the switch inside the server. This resulted in significant signal loss at high speeds. To minimize this loss, Silicon Photonics components have been moved closer to the server’s switch, shortening the electrical transmission path. Consequently, the original pluggable modules now only contain optical fibers.

This approach aligns with the actively developing “Co-Packaged Optics” (CPO) technology in the industry. The main idea is to assemble electronic integrated circuits (EIC) and photonic integrated circuits (PIC) onto the same substrate, creating a co-packaged board that integrates chips and modules. This co-packaging, known as CPO light engines (depicted in figure “d” below), replaces optical transceivers and brings optical engines closer to CPU/GPU chips (depicted in figure “d” as chips). This reduces transmission paths, minimizes transmission loss, and reduces signal delay.

According to ITRI, this technology reduces costs, increases data transmission by over 8 times, provides more than 30 times the computing power, and saves 50% in power consumption. However, the integration of chipsets is still a work in progress, and refining CPO technology will be the next important step in the development of Silicon Photonics.

• Solving the CPO Bottleneck and Beyond – Silicon Photonics Stage 2: Addressing CPU/GPU Transmission Issues

Currently, Silicon Photonics primarily addresses the signal delay challenges of plug-in modules. As technology progresses, the next stage will involve solving the electrical signal transmission issues between CPUs and GPUs. Academics point out that chip-to-chip communication is primarily based on electrical signals. Therefore, the next step is to enable internal chip-to-chip communication between GPUs and CPUs using optical waveguides, converting all electrical signals into optical signals to accelerate AI computations and address the current computational bottleneck.

• Silicon Photonics Ultimate Stage 3: The Arrival of the All-Optical Network (AON) Era

As technology advances even further, we will usher in the era of the “All-Optical Network” (AON). This means that all chip-to-chip communication will rely on optical signals, including random storage, transmission, switching, and processing, all of which will be transmitted as optical signals. Japan has already been actively implementing Silicon Photonics in preparation for the full transition to all-optical networks in this context.

Where Does Silicon Photonics Currently Face Technological Challenges?

Currently, Silicon Photonics faces several challenges related to component integration. First and foremost is the issue of communication. Dr. Fang Yen Hsiang provides an example: semiconductor manufacturers understand electronic processes, but because the performance of photonic components is sensitive to factors such as temperature and path length, and because linewidth and spacing have a significant impact on optical signal transmission, a communication platform is needed. This platform would provide design specifications, materials, parameters, and other information to facilitate communication between electronic and photonic manufacturers.

Furthermore, Silicon Photonics is currently being applied in niche markets, and various packaging processes and material standards are still being established. Most of the wafer foundries that provide Silicon Photonics chip fabrication belong to the realm of customized services and may not be suitable for use by other customers. The lack of a unified platform could hinder the development of Silicon Photonics technology.

In addition to the lack of a common platform, high manufacturing costs, integrated light sources, component performance, material compatibility, thermal effects, and reliability are also challenges in Silicon Photonics manufacturing processes. With ongoing technological progress and innovation, it is expected that these bottlenecks will be overcome in the coming years to a decade.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: Google)

According to a report by Taiwanese media Money DJ, after establishing a stable position as a major supplier for NVIDIA GPU baseboard, Wistron has secured orders for AMD MI300 baseboards. Reliable sources indicate that Wistron has expanded its involvement beyond AMD baseboards and entered the module assembling segment.

In addition to NVIDIA and AMD, Wistron has also entered the Intel AI chip module and baseboard supply chain, encompassing orders from the three major AI chip manufacturers.

The NVIDIA AI server supply chain includes GPU modules, GPU baseboards, motherboards, server systems, complete server cabinets, and more. Wistron holds a significant share in GPU baseboard supply and is also involved in server system assembly.

Currently, NVIDIA commands a 70% market share in AI chips, but various chip manufacturers are eager to compete. Both AMD and Intel have introduced corresponding solutions. While Wistron was previously rumored to have entered AMD baseboard supply, it has also ventured into AMD GPU module assembling, serving as the sole source, according to reliable sources.

Regarding the news of Wistron’s involvement in AMD and Intel chip manufacturing, the company has chosen not to respond to market rumors.

(Photo credit: Google)

In the realm of specifications competition, desktop computers continue to possess numerous irreplaceable advantages. These include ease of upgrading, superior heat dissipation capabilities, and robust and durable construction, resulting in extended usage lifespans. As a result, desktop computers maintain a steadfast market demand. Due to the ease of component replacement in desktops, expandability remains a significant advantage for PC gamers. For creators and business professionals, desktop computers satisfy extensive external connectivity needs while offering superior heat dissipation. Furthermore, owing to the size limitations of laptops, desktop computers continue to provide a more comfortable user experience during prolonged usage.

Windows 10 Exit and Hardware Updates Set to Drive 2024 Upgrade Trend

In the latter half of 2022, brands and retailers aggressively cleared their inventories, a trend that continued into 2023, resulting in a sustained challenging period for the PC market. In recent years, the PC market has approached saturation, making it difficult to drive market growth through sheer quantity. Consequently, brand manufacturers have focused on business, gaming, and creator products. However, PCs inherently belong to a cyclical terminal market. With the Windows 10 operating system set to retire in October 2025 and Windows 11’s heightened hardware specifications requirements, products released before 2017 will require replacements. Additionally, it is anticipated that companies like Intel, AMD, and NVIDIA will gradually unveil new products in the latter half of 2023. This, coupled with the demands of the new operating system, is expected to trigger a noticeable upgrade trend among consumers, ultimately providing a glimmer of hope for the PC market. (Image credit: Unsplash_Alienwaregaming)

As applications like AIGC, 8K, AR/MR, and others continue to develop, 3D IC stacking and heterogeneous integration of chiplet have become the primary solutions to meet future high-performance computing demands and extend Moore’s Law.

Major companies like TSMC and Intel have been expanding their investments in heterogeneous integration manufacturing and related research and development in recent years. Additionally, leading EDA company Cadence has taken the industry lead by introducing the “Integrity 3D-IC” platform, an integrated solution for design planning, realization, and system analysis simulation tools, marking a significant step towards 3D chip stacking.

Differences between 2.5D and 3D Packaging

The main difference between 2.5D and 3D packaging technologies lies in the stacking method. 2.5D packaging involves stacking chips one by one on an interposer or connecting them through silicon bridges, primarily used for assembling logic processing chips and high-bandwidth memory. On the other hand, 3D packaging is a technology that vertically stacks chips, mainly targeting high-performance logic chips and SoC manufacturing.

CPU and HBM Stacking Demands

With the rapid development of applications like AIGC, AR/VR, and 8K, it is expected that a significant amount of computational demand will arise, particularly driving the need for parallel computing systems capable of processing big data in a short time. To overcome the bandwidth limitations of DDR SDRAM and further enhance parallel computing performance, the industry has been increasingly adopting High-Bandwidth Memory (HBM). This trend has led to a shift from the traditional “CPU + memory (such as DDR4)” architecture to the “Chip + HBM stacking” 2.5D architecture. With continuous growth in computational demand, the future may see the integration of CPU, GPU, or SoC through 3D stacking.

3D Stacking with HBM Prevails, but CPU Stacking Lags Behind

HBM was introduced in 2013 as a 3D stacked architecture for high-performance SDRAM. Over time, the stacking of multiple layers of HBM has become widespread in packaging, while the stacking of CPUs/GPUs has not seen significant progress.

The main reasons for this disparity can be attributed to three factors: 1. Thermal conduction, 2. Thermal stress, and 3. IC design. First, 3D stacking has historically performed poorly in terms of thermal conduction, which is why it is primarily used in memory stacking, as memory operations generate much less heat than logic operations. As a result, the thermal conduction issues faced by current memory stacking products can be largely disregarded.

Second, thermal stress issues arise from the mismatch in coefficients of thermal expansion (CTE) between materials and the introduction of stress from thinning the chips and introducing metal layers. The complex stress distribution in stacked structures has a significant negative impact on product reliability.

Finally, IC design challenges from a lack of EDA tools, as traditional CAD tools are inadequate for handling 3D design rules. Developers must create their own tools to address process requirements, and the complex design of 3D packaging further increases the design, manufacturing, and testing costs.

How EDA Companies Offer Solutions

Cadence, during the LIVE Taiwan 2023 user annual conference, highlighted its years of effort in developing solutions. They have introduced tools like the Clarity 3D solver, Celsius thermal solver, and Sigrity Signal and Power Integrity, which can address thermal conduction and thermal stress simulation issues. When combined with Cadence’s comprehensive EDA tools, these offerings contribute to the growth of the “Integrity 3D-IC” platform, aiding in the development of 3D IC design.

“3D IC” represents a critical design trend in semiconductor development. However, it presents greater challenges and complexity than other projects. In addition to the challenges in Logic IC design, there is a need for analog and multi-physics simulations. Therefore, cross-platform design tools are indispensable. The tools provided by EDA leader Cadence are expected to strengthen the 3D IC design tool platform, reducing the technological barriers for stacking CPU, GPU, or SoC to enhance chip computing performance.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC)

According to Taiwan’s TechNews report, Lu Donghui, Chairman of Micron Technology Taiwan, stated that in response to the growing demand in the AI market, Micron Technology Taiwan will continue to invest in advanced processes and packaging technologies to produce High Bandwidth Memory (HBM) products. Micron Technology Taiwan is the only Micron facility globally with advanced packaging capabilities.

Lu Donghui, speaking at a media event, mentioned that Micron had previously introduced the industry’s first 8-layer stack (8-High) 24GB HBM3 Gen 2 product, which is now in the sampling phase. This product boasts a bandwidth exceeding 1.2TB/s and a transmission rate exceeding 9.2Gb/s, which is 50% higher than other HBM3 solutions on the market. Micron’s HBM3 Gen 2 product offers 2.5 times better energy efficiency per watt compared to previous generations, making it ideal for high-performance AI applications.

Micron’s HBM3 Gen 2 memory products are manufactured using the most advanced 1-beta process technology in Taiwan and Japan. Compared to the previous 1-alpha process, the 1-beta process reduces power consumption by approximately 15% and increases bit density by over 35%, with each chip offering a capacity of up to 16Gb. Through Micron’s advanced packaging technology, the 1-beta process memory chips are stacked in 8 layers, and the complete HBM3 Gen 2 chips are packaged and sent to customers’ specified semiconductor foundries like TSMC, Intel, Samsung, or third-party packaging and testing facilities for GPUs, CPUs.

Lu Donghui highlighted that Taiwan’s robust semiconductor manufacturing ecosystem makes it the exclusive hub for Micron’s advanced packaging development worldwide. By combining this ecosystem with Micron’s offerings, they can provide customers with comprehensive solutions to meet market demands. While HBM products represent a relatively small portion of the overall memory market, their future growth potential is significant, with expectations to capture around 10% of the entire memory market in the short term.

(Photo credit: Micron)