Intel Corporation today announced that it has mutually agreed with Tower Semiconductor to terminate its previously disclosed agreement  to acquire Tower due to the inability to obtain in a timely manner the regulatory approvals required under the merger agreement, dated Feb. 15, 2022. In accordance with the terms of the merger agreement and in connection with its termination, Intel will pay a termination fee of $353 million to Tower.

In response to this development, TrendForce provides the following analysis:

As previously mentioned by TrendForce, Intel’s active entry into the semiconductor foundry market has presented challenges. These include:

Diversification of Manufacturing Expertise: Intel, historically focused on manufacturing CPUs, GPUs, FPGAs, and peripheral I/O chips, lacks the specialized fabrication processes possessed by other foundries. The success of acquiring Tower to expand its product line and market presence remains crucial.

Operational Segmentation: Apart from financial divisions, the division of physical facilities and actual production capacity must be strategically managed. Successfully emulating models like AMD/GlobalFoundries or Samsung LSI/Samsung Foundry, where there is a clear distinction between foundry and client, is essential. Simultaneously, Intel faces challenges in preventing orders from its significant client, the Intel Design Department, from flowing outward.

The official termination of the Tower acquisition plan introduces greater uncertainties and challenges for Intel in the competitive foundry market. In an industry marked by heightened competition, having dominance in specialized process technologies and diversified production lines is pivotal for sustaining profitability amid industry downturns. Without the assistance of Tower’s established specialized processes, Intel’s strategic approach and technology development in the foundry business will be worth monitoring.

(Photo credit: Intel)

As per a report from Taiwan’s TechNews,” TSMC, Samsung, and Intel have been actively deploying Backside Power Delivery Network (BSPDN) strategies recently, and have announced plans to incorporate BSPDN into their logic chip development roadmap. For instance, Samsung intends to implement BSPDN technology in its 2-nanometer chips, a move unveiled at the VLSI Symposium in Japan.

According to imec, BSPDN aims to alleviate the congestion issues faced by front-end logic chips in later-stage processes. Through Design Technology Co-Optimization (DTCO), more efficient wire designs are achieved in standard cells, aiding in the downsizing of logic standard cell.

In essence, BSPDN can be seen as a refinement of chiplet design. The conventional approach, where logic circuits and memory modules are integrated, is transformed into a configuration with logic functions on the front and power or signal delivery from the back.

While the traditional method of front-side wafer power delivery achieves its purpose, it leads to decreased power density and compromised performance. Nevertheless, the new BSPDN technique has not yet been adopted by foundries.

Samsung claims that, compared to the conventional method, BSPDN reduces area by 14.8%, providing more chip space for additional transistors and improved overall performance. Wire lengths are also cut by 9.2%, reducing resistance, allowing greater current flow, and thereby lowering power consumption while enhancing power transmission efficiency.

In June of this year, Intel also introduced its BSPDN-related innovations under the name ‘PowerVia.’ Team Blue plans to utilize this approach in the Intel 20A process, potentially achieving a chip utilization rate of 90%.

Intel believes PowerVia will address interconnect bottlenecks in silicon architecture, enabling continuous transmission through backside wafer powering. The company anticipates incorporating this novel approach into its Arrow Lake CPUs slated for release in 2024.

Furthermore, according to Taiwan’s supply chain sources, TSMC remains on track to launch its 2-nanometer process in 2025, with mass production expected in the latter half of the year in Hsinchu’s Baoshan. The company’s N2P process, planned for 2026, will feature BSPDN technology.

(Photo credit: Samsung)

According to the news from Mydrivers.com, TSMC announced its ambitious plans for constructing cutting-edge 4nm and 3nm chip fabs in the United States. The move is expected to generate tens of thousands of job opportunities in the US job market. However, TSMC’s timeline for commencing production at its inaugural 4nm fab has been pushed back from 2024 to 2025. The attributed cause behind this delay is the insufficient availability of skilled American workers, causing setbacks in equipment installation.

This situation has led to a heated dispute between TSMC and local labor unions. TSMC’s assertion of a skilled worker deficit in the US has sparked disagreement from the unions. They assert that TSMC’s stance is a pretext for bringing in lower-wage overseas labor to vie for domestic employment opportunities. TSMC, on the other hand, refutes these claims, emphasizing that employing local staff on assignment doesn’t undermine their US-based operations or recruitment efforts.

Apart from the skill-related quandary, the delay in TSMC’s factory plans may have an underlying factor – the scorching conditions in Phoenix, Arizona. Sources report that the city has experienced an unbroken streak of over 20 days with temperatures hovering around 43 degrees Celsius. Notably, this heat wave has raised internal questioning within TSMC about the wisdom of selecting a desert-adjacent location for their facility.

According to this industry insider, the intense heat seemingly played a role in impeding progress. The sweltering climate of over 40 degrees Celsius undoubtedly hampers worker productivity, particularly for outdoor tasks.

The informer indicated that TSMC had an alternative option when choosing a location for its US facility. Aside from Arizona, they could have set up shop in Portland, the capital of Oregon, which is also a hub for the semiconductor industry. However, TSMC’s rationale for settling in Arizona remains undisclosed.

Notably, Phoenix, Arizona, is also a focal point for Intel’s chip investments, with the company injecting 20 billion USD into the establishment of new wafer fabs over the past couple of years.

(Source: https://news.mydrivers.com/1/928/928753.htm)

As semiconductor process technology nears known physical limits, the spotlight among major industry players is shifting towards the development of advanced packaging. Concurrently, the rise of applications like artificial intelligence and AIGC has propelled the concept of advanced packaging into a new technological wave. In the midst of the semiconductor industry’s global competition, securing more orders has become a core objective for major players.

A Competitive Landscape in Advanced Packaging

The competition in advanced packaging technology is intensifying, with companies pouring substantial investments into the field, resulting in a landscape of vigorous competition. Various packaging technologies have emerged, with notable offerings from industry giants such as TSMC, Intel, and Samsung.

TSMC introduced 3DFabric, an integration of its TSMC-SoIC front-end technology with CoWoS and InFO back-end technologies, providing maximum flexibility for diverse innovative product designs.

Intel, on the other hand, features its 2.5D EMIB and 3D Foveros packaging technologies. EMIB is applied in the connection of logic chips and high-bandwidth memory, as seen in the Intel Xeon Max series and Intel Data Center GPU Max series.

Foveros allows top dies to overcome size limitations and accommodate more top and base dies, connected through copper pillars to reduce potential interference from through-silicon vias (TSVs).

Samsung also exhibits strong competitiveness in advanced packaging, with its 2.5D I-Cube4 and H-Cube, along with 3D X-Cube packaging technologies, achieving breakthroughs in multi-chip interconnects and integration.

Samsung’s I-Cube4, for example, integrates four HBM stack dies and one core compute IC on the silicon interposer layer, while H-Cube enhances packaging area through the stacking of HDI PCBs to accommodate designs with six or more HBM stack dies.

Advantages of the Three Giants

In recent years, the three semiconductor giants have directed substantial capital expenditure towards advanced packaging. Their diverse technological developments and marketing strategies are poised to ignite a global battle in the semiconductor advanced packaging industry.

TSMC holds the advantage with its dominant wafer process technology and an end-to-end comprehensive service approach. Coupled with Taiwan’s robust semiconductor ecosystem, TSMC leads the way in the advanced packaging domain.

Intel, while slightly trailing TSMC in advanced process technology, matches it in advanced packaging capabilities. Emphasizing flexible foundry services, Intel allows clients to mix and match its wafer manufacturing and packaging offerings. With manufacturing facilities scattered worldwide, Intel leverages geographic advantages, particularly in Western countries, to expand capacity and services, leading to anticipated gains in the future.

Samsung, like TSMC, offers end-to-end services, but its packaging technology lags behind TSMC’s. It secures a share in constrained supply situations. Notably, Samsung, in June 2022, was ahead of TSMC in unveiling the innovative GAA 3nm process, and is poised to combine it with 3D packaging technology, potentially marking a pivotal point in the next semiconductor generation.

With semiconductor technology’s continuous evolution and surging market demand, the competition among the three giants in advanced packaging will remain fierce. While wafer fabs currently prioritize processes, the next three to five years are expected to witness a gradual shift towards advanced packaging. Different packaging technologies and marketing strategies will ultimately determine companies’ positions and influence in the market.

(Photo credit: TSMC)

Read more:

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• ASE, Amkor, UMC and Samsung Getting a Slice of the CoWoS Market from AI Chips, Challenging TSMC

Leading semiconductor companies are making significant strides in global expansion with the announcement of two new fabrication facilities. TSMC is set to greenlight a factory in Germany, while GlobalFoundries plans to establish its first 12-inch wafer plant in Singapore.

TSMC’s Bold Move: Germany’s Green Light

TSMC from its presence in the USA, China (Shanghai and Nanjing), to Japan (Kumamoto City), TSMC’s global manufacturing footprint is expanding. Reuters reported on August 7 that TSMC’s board is inclined to approve the construction of a plant in Dresden, Germany. The German government pledges a substantial 5 billion euros (about $5.49 billion USD) to support the facility. However, the German Ministry of Economy refrains from commenting on the matter.

TSMC has been negotiating with the Saxony German state since 2021 to establish a collaborative FAB plant. In partnership with Bosch, Infineon, and Onsemi, TSMC aims to utilize the Dresden plant primarily for automotive chip production. Pending board approval, this venture could involve financing discussions with Berlin, ultimately requiring European Commission endorsement. TSMC, Intel, and Wolfspeed stand out among chip manufacturers seeking government assistance for European manufacturing ventures.

GlobalFoundries Poised to Build 12-Inch Wafer Plant in Singapore

According to udn.com, GlobalFoundries is set to make a substantial investment in the establishment of a 12-inch wafer fabrication plant in Singapore. The project’s funding could exceed NT$100 billion (approximately $3.2 billion USD). Reports suggest that this Singaporean facility will focus on producing 28-nanometer chips, with a potential completion date as early as 2026.

Industry experts note that GlobalFoundries’ move to set up a 12-inch facility in Singapore implies a significant shift in the competitive landscape. TSMC, UMC, PSMC, and GlobalFoundries – the four major semiconductor foundries – will all possess 12-inch production capabilities. Additionally, each of these companies has international expansion plans for such facilities. Notably, TSMC’s ventures span across the USA and Japan, UMC, and GlobalFoundries are both targeting Singapore, while PSMC’s strategy involves establishing a plant in Japan in collaboration with local partners.

Major Manufacturers Expand Against the Current Downturn

TSMC has been proactive in its expansion strategy, unveiling plans for ten new facilities in the past two years. These include 5 wafer plants and 2 advanced packaging facilities in Taiwan, alongside 3 overseas wafer plants. Despite the industry’s current challenges, TSMC’s expansion momentum remains strong, driven by a heightened focus on global manufacturing diversity.

TSMC is well aware of the potential risks tied to significant expansion efforts. In its latest annual report, the company acknowledges that expanding on a global scale demands substantial resources, highlighting possible challenges like rising costs, workforce shortages, disasters, land scarcity, cyber threats, government support, cultural differences, intellectual property protection, and tax variations.

Expanding during a semiconductor downturn has become a strategic approach for the foundry players. Typically, a fab construction takes 2 to 4 years, with equipment installation lasting 0.5 to 1 year and production ramp-up stretching 1 to 2 years. Looking ahead, semiconductor foundries are gearing up for a fresh wave of capacity release throughout 2024 and 2025.

Despite the industry’s ongoing slump, encouraging signs suggest that the downturn might be reaching its conclusion. Industry experts are cautiously optimistic, anticipating the arrival of the next upswing in the cycle.

(Source: https://mp.weixin.qq.com/s/4Xu_uc58kG85E_6R4Y3qhQ)