In the ongoing global race for advanced semiconductor technology, TSMC, the leader in semiconductor manufacturing services, continues its strides towards 2nm project. The Hsinchu’s Baoshan plant is set to commence equipment installation in Q2 2024, with mass production scheduled for Q4 2025, starting with a monthly output of around 30,000 wafers. Meanwhile, TSMC fab in Kaohsiung is organizing for N2P mass production, featuring backside power supply tech, a year after N2’s debut.

According to a report by Taiwan’s Money DJ, as previously shared by TSMC, the N2 process introduces a backside power rail solution, ideal for high-performance computing (HPC) applications. The backside power rail promises a 10% to 12% speed boost and a 10% to 15% logic density improvement. The aim is to introduce backside power rail to customers in H2 2025, aligning with supply chain reports.

Notably, Intel led the transition from planar transistors to FinFET, and now, with evolving technologies like MBCFET, BSPDN (Backside Power Delivery Network) based on Gate-All-Around (GAA) FET. Major players such as TSMC, Samsung, and Intel actively compete for leadership in the next-gen GAA technology, and have further presented promising and proactive technology roadmaps.

According to Samsung Semiconductor’s plans, they target to implement the 2nm process into mass production by 2025, with 1.4nm scheduled for 2027. Intel, adopting RibbonFET transistor architecture based on GAA technology, anticipates pilot production of the 20A version in H1 2024 and mass production of the 18A in 2025.

Source to UDN, the DRAM market has been buzzing with positive developments lately, and may get a chance to see an upturn by the end of the year. Among the key factors driving this optimism is the DDR5 specification DRAM, which is poised to capitalize on opportunities in AI servers and laptops next year, gradually increasing demand.

After more than a year of corrections, the DRAM market is finally showing signs of improvement. Major DRAM manufacturers like Samsung and SK Hynix are still reducing production capacity, but their focus is primarily on DDR4 specification DRAM. Industry sources suggest that Samsung, in response to the growing demand for DDR5 DRAM, is set to significantly ramp up DDR5 production in the fourth quarter of this year, anticipating strong order demand next year.

In fact, such as Intel and AMD are planning to introduce new platforms next year that will support DDR5 specification DRAM, indicating a gradual decline in DDR4 demand. Beyond the consumer market, the server market is expected to experience a substantial surge in DDR5 demand, driven by the imminent launch of Intel’s fifth-generation server platform, Emerald Rapids, which fully supports DDR5. As AI server demand gains momentum, DDR5 demand is poised to enter a high-growth phase.

(Source: https://money.udn.com/money/story/5612/7488629 ; Image credit: Micron)

The Silicon Photonics topic is heating up as major companies race to address the data transfer speed between chips. Intel’s Silicon Photonics project has a leading advantage, while TSMC is collaborating with major customers Nvidia and Broadcom, investing 200 research and development personnel. They aim to complete the project in the second half of 2024, with production set to begin in 2025.

According to Taiwan’s Commercial Times, Luo Huaijia, the Executive Director of the Photonics Industry and Technology Development Association (PIDA) in Taiwan, stated that silicon photonics technology has always been a crucial focus in the field of photonics. Photonics products are evolving towards being compact, lightweight, energy-efficient, and power-saving.

Among Taiwan’s semiconductor fabs, TSMC stands out with its COUPE, which provides heterogeneous integration of photonic integrated circuits (PIC) and electronic integrated circuits (EIC), reducing energy consumption by 40%. TSMC is rumored to deploy a 200-person R&D team, collaborating with international major clients for joint development. Consequently, following the completion of its Hsinchu plant, TSMC invested NT$90 billion in constructing a new packaging plant in Tongluo, Miaoli, recognizing the significant demand and potential in heterogeneous integration.

Luo Huaijia pointed out that silicon photonics uses semiconductor technology to create a platform with optical properties, with the goal of integrating light and telecommunications signals. This involves packaging traditional optical components, including optical waveguides, light-emitting elements, and transceiver modules, together, thus also involving heterogeneous packaging.

As early as 2002, Intel publicly conducted research in the field of “Silicon Photonics,” but at that time, the data volume could be handled with copper wire transmission. Luo Huaijia believes that with the exponential increase in AI computing power, data processing will start in the gigabyte range, prompting companies to invest heavily in development.

Luo Huaijia analyzed that currently, GlobalFoundries is likely the first company to provide wafer foundry services for manufacturing optical fiber transceivers, using FD-SOI technology integration solutions. Intel also currently offers a 400Gb/s optical fiber transceiver solution. In addition to their own ASICs or FPGAs, this technology is applied to Switch ICs. Intel even plans to expand its silicon photonics solution into the automotive market, using it in Mobileye’s optical radar by 2025.

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(Photo credit: ITRI)

According to a report by China’s Jiwei, Intel’s recent sale of a 10% stake in IMS to TSMC has not generated much buzz in the industry. Most industry insiders view this transaction positively, considering the importance of IMS and TSMC’s vertical integration.

However, why did TSMC decide to purchase a 10% stake in IMS now, when the two companies have been collaborating on research and development for a decade?

The Importance of IMS

When it comes to semiconductor equipment, Dutch lithography giant ASML is a well-known name. However, it’s worth noting that in the semiconductor manufacturing process, the multi-beam mask writer provided by IMS is also crucial. Established in Vienna in 1985, IMS primarily focuses on advanced process node photomask manufacturing.

The significance of photomasks is undeniable. As processes evolve, the demand for photomasks continues to rise. It’s understood that the 14nm process requires approximately 60 photomasks, while the 7nm process demands around 80 to even hundreds of them. Correspondingly, photomask prices have been steadily climbing. According to IBS data, photomask costs are approximately $5 million in the 16/14nm process, but in the 7nm process, they rapidly increase to $15 million.

Within the total cost of photomasks, which includes equipment like writers and inspection tools, raw materials like quartz and photoresist, as well as software like OPC and MDP, the writer’s contribution is significant.

Experts analyze that without IMS’ multi-beam mask writer, all EUV process technologies would come to a halt, rendering ASML’s EUV equipment less useful. Furthermore, as lithography technology advances towards High-NA EUV, its progress relies on sophisticated mask writing tools. With advanced processes continually pushing forward, IMS technology will play a crucial role.

Perhaps recognizing the importance of mask writers early on, Intel invested in IMS as early as 2009 and ultimately acquired it in 2015. After years of effort, IMS has secured a dominant position in the multi-beam mask writer market, with reported its employees and capacity quadrupling since the acquisition, bringing substantial profits to Intel.

Delving deeper, there is a longstanding connection between TSMC and IMS.

Since 2012, TSMC has been collaborating with IMS to develop multi-beam mask writers for advanced technology nodes. Kevin Zhang, Senior Vice President, Business Development and Overseas Operations Office at TSMC, stated that this investment will continue their long-term partnership to accelerate innovation and achieve deeper cross-industry collaboration.

Regarding TSMC’s investment in IMS, research institutions have pointed out that TSMC has always pursued a vertical integration strategy to master various aspects of technology and resources in the semiconductor manufacturing field. Particularly noteworthy is TSMC’s in-house mask manufacturing, where the precision and quality of masks are crucial for chip performance. IMS can be seen as a key supplier to TSMC, providing critical products.

Industry experts also point out that TSMC’s decision may help them gain an advantage in the 2nm competition. As the competition in the 2nm transitions from three competitors to four, involving TSMC, Samsung, Intel, and Japan’s Rapidus, 2025 is poised to be a pivotal year. In the era of 2nm, not only will the use of ASML’s next-generation High-NA EUV equipment be essential, but also harnessing the power of mask writers. TSMC’s investment in IMS could solidify their collaboration and help them pull ahead of other competitors.

(Photo credit: IMS)

According to a report from Taiwan’s Economic Daily, TSMC’s 3-nanometer technology has attracted another heavyweight client. Following Apple and MediaTek, it is rumored that Qualcomm will also commission TSMC to produce its next-generation 5G flagship chip using the 3-nanometer process. The chip is expected to be unveiled in late October, making Qualcomm the third client for TSMC’s 3-nanometer technology.

In response to these rumors, Qualcomm has not provided any comments, while TSMC has chosen to remain silent. Industry experts speculate that TSMC’s 3-nanometer technology will likely attract additional orders from major players such as NVIDIA and AMD in the future. With various leading-edge fabs continuously seeking TSMC’s services, it appears that TSMC’s 3-nanometer technology remains the top choice for international giants.

Last year, Qualcomm unveiled its annual 5G flagship chip, the “Snapdragon 8 Gen 2,” manufactured using TSMC’s 4-nanometer process. The previous-generation Snapdragon “8 Gen 1” was produced using Samsung’s 4-nanometer process, but it encountered issues related to heat dissipation. Consequently, Qualcomm released an upgraded version, the “Snapdragon 8+ Gen 1,” using TSMC’s 4-nanometer process.

Qualcomm has traditionally adopted a multi-supplier strategy for semiconductor manufacturing. It is rumored in the industry that Qualcomm has privately informed its smartphone brand customers about the upcoming next-generation 5G flagship chip, the “Snapdragon 8 Gen 3,” expected to be announced in late October. This chip will be available in two process versions: TSMC’s 4-nanometer (N4P) and 3-nanometer (N3E).

(Photo credit: TSMC)