Semiconductor process technology is nearing the boundaries of known physics. In order to continually enhance processor performance, the integration of small chips (chiplets) and heterogeneous Integration has become a prevailing trend. It is also regarded as a primary solution for extending Moore’s Law. Major industry players such as TSMC, Intel, Samsung, and others are vigorously developing these related technologies.

What are SoC, SiP, and Chiplet?

To understand Chiplet technology, we must first clarify two commonly used terms: SoC and SiP. SoC (System on Chip) involves redesigning multiple different chips to utilize the same manufacturing process and integrating them onto a single chip. On the other hand, SiP (System in Package) connects multiple chips with different manufacturing processes using heterogeneous integration techniques and integrates them within a single packaging form.

Chiplet technology employs advanced packaging techniques to create a SiP composed of multiple small chips. It integrates small chips with different functions onto a single substrate through advanced packaging techniques. While Chiplets and SiPs may seem similar, Chiplets are essentially chips themselves, whereas SiP refers to the packaging form. They have differences in functionality and purpose.

Chiplets: Today’s Semiconductor Development Trend

The design concept of Chiplet technology offers several advantages over SoC, notably in significantly improving chip manufacturing yield. As chip sizes increase to enhance performance, chip yield decreases due to the larger surface area. Chiplet technology can integrate various smaller chips with relatively high manufacturing yields, thus enhancing chip performance and yield.

Furthermore, Chiplet technology contributes to reduced design complexity and costs. Through heterogeneous integration, Chiplets can combine various types of small chips, reducing integration challenges in the initial design phase and facilitating design and testing. Additionally, since different Chiplets can be independently optimized, the final integrated product often achieves better overall performance.

Chiplets have the potential to lower wafer manufacturing costs. Apart from CPUs and GPUs, other units within chips can perform well without relying on advanced processes. Chiplets enable different functional small chips to use the most suitable manufacturing process, contributing to cost reduction.

With the evolution of semiconductor processes, chip design has become more challenging and complex, leading to rising design costs. In this context, Chiplet technology, which simplifies design and manufacturing processes, effectively enhances chip performance, and extends Moore’s Law, holds significant promise.

Applications and Development of Chiplets

In recent years, global semiconductor giants like AMD, TSMC, Intel, NVIDIA, and others have recognized the market potential in this field, intensively investing in Chiplet technology. For example, AMD’s recent products have benefited from the ‘SiP + Chiplet’ manufacturing approach. Moreover, Apple’s M1 Ultra chip achieved high performance through a customed UltraFusion packaging architecture. In academia, institutions like the University of California, Georgia Tech, and European research organizations have begun researching interconnect interfaces, packaging, and applications related to Chiplet technology.

In conclusion, due to Chiplet technology’s ability to lower design costs, reduce development time, enhance design flexibility and yield, while expanding chip functionality, it is an indispensable solution in the ongoing development of high-performance chips.

This article is from TechNews, a collaborative media partner of TrendForce.

According to Taiwan’s TechNews report, Intel has revealed the architecture and supply schedule of the new generation data center Xeon processors, Sierra Forest and Granite Rapids. They are also set to unveil the consumer processor codenamed Meteor Lake in mid-September. However, with the semiconductor market’s current weak recovery, the impact of Intel’s new processors on driving upgrades and benefiting Taiwanese supply chain manufacturers remains uncertain, making it a market focal point.

Regarding the consumer-oriented Meteor Lake processor, industry sources suggest that it will not only be the first to adopt “Intel 4” technology, but also the first to utilize EUV lithography for cost reduction in mass-producing CPU tiles. TSMC will assist in production using the 5/6 nanometer process for graphics chip modules (GFX tile), system chip modules (SoC tile), and input/output chip modules (IOE tile), aiming for higher yields to decrease production costs.

Furthermore, the Meteor Lake processor shifts from traditional monolithic chip design to chiplet technology. After separating functions like graphics, system, and I/O chips, it employs the 3D Foveros advanced packaging technology. Through Foveros interconnects, multiple chiplets are vertically stacked into one chip. This approach not only increases the yield of critical modules but also reduces costs, granting Intel greater flexibility in rapidly creating next-generation chip capacities.

For the upcoming Meteor Lake processor, its direct beneficiary is undoubtedly TSMC, which assists in producing graphics chip modules, system chip modules, and input/output chip modules using the 5/6 nanometer process. This collaboration not only boosts revenue but also maintains the ongoing partnership with Intel.

However, despite Taiwanese foundries and board manufacturers securing orders for Intel’s new-generation processors, the current economic environment remains unfavorable. With a cautious and conservative outlook on consumer spending in the global market, the launch of Intel’s new products could either boost supply chain revenue or lead to increased inventory in the next phase, requiring further observation.

(Photo credit: Intel)

As reported by TechNews, a media partner of TrendForce, Southeast Asia and India, equipped with the advantages of demographic dividends, strategic geographic positioning, manufacturing capabilities, and rapidly growing economic markets, have undoubtedly emerged as the preferred destinations for the technology industry amidst the global supply chain transition prompted by geopolitical factors.

As supply chains actively seek production bases beyond China and governments introduce incentive programs and policy restrictions for localized supply, various Southeast Asian countries have become key hubs for different sectors. Vietnam has become a focal point for consumer electronics manufacturing such as laptops, watches, and headphones, while Thailand has become a preferred choice for automotive-related supply chains. Thailand and Malaysia host assembly bases for servers, and India is set to become a crucial hub for mobile phone production.

Apart from the movement of end-product assembling, the shift in the semiconductor supply chain has also garnered attention. With TSMC, Samsung, and Intel relocating wafer fabrication plants to the United States, Europe, and other regions, a significant cluster of semiconductor backend testing and packaging has been forming in Malaysia.

What Advantages Does Malaysia Offer to Attract Multinational Semiconductor Companies’ Investment, and What Is the Current Industry Landscape?

Firstly, Malaysia boasts higher education standards than neighboring countries. Among ASEAN nations, only Singapore and Malaysia employ the British legal system, providing a competitive edge for many companies’ location choices. Secondly, in terms of language proficiency, Malaysian citizens predominantly use English, Mandarin, and Malay, facilitating smooth communication with global enterprises.

Thirdly, Malaysia is home to two major ports—Port Klang and Port of Tanjung Pelepas—both ranked among the world’s top 15 ports, with substantial container handling capacity and global reach.

Lastly, the state of Penang stands as a semiconductor hub for Malaysia, having nurtured the semiconductor industry for several decades and holding a technological lead. Often referred to as the “Silicon Valley of the East,” Penang has primarily focused on producing chips for electronics, computers, and mobile phones. However, with the growing adoption of electric vehicles, the demand for automotive chips has surged. Concurrently, the green energy trend has propelled the need for solar panels and renewable energy sources. This optimistic outlook for the semiconductor industry has once again attracted numerous companies to establish facilities and expand production capacity.

Current State of Malaysia’s Semiconductor Industry

Looking at the recent dynamics of corporations over the past two years, the trend is evident that Malaysia is evolving into a center for semiconductor backend testing and packaging. Major global players have announced plans to establish or expand operations in Penang. Intel, for example, announced a $6.46 billion investment in Malaysia in 2021, focusing on advanced packaging capabilities in Penang and Kedah.

Texas Instruments declared its intent to construct semiconductor testing and packaging plants in Kuala Lumpur and Malacca, with a total investment of up to $2.7 billion. Infineon is investing $5.45 billion to expand existing facilities, producing silicon carbide and entering the electric vehicle sector. Bosch Group is investing $358 million in stages to strengthen its semiconductor supply chain position in Penang. ASE Technology Holding, also began construction on a new testing facility in Penang at the end of last year.

With the influx of semiconductor giants, Malaysia’s position in the semiconductor industry has become increasingly critical. The distinct production base trends, aligned with the strengths of various Southeast Asian countries, have become clear. The restructuring of supply chains and the transformation of production centers undoubtedly remain the focus and challenge for global companies.

(Photo credit: ASE)

Intel Corporation today announced that it has mutually agreed with Tower Semiconductor to terminate its previously disclosed agreement  to acquire Tower due to the inability to obtain in a timely manner the regulatory approvals required under the merger agreement, dated Feb. 15, 2022. In accordance with the terms of the merger agreement and in connection with its termination, Intel will pay a termination fee of $353 million to Tower.

In response to this development, TrendForce provides the following analysis:

As previously mentioned by TrendForce, Intel’s active entry into the semiconductor foundry market has presented challenges. These include:

Diversification of Manufacturing Expertise: Intel, historically focused on manufacturing CPUs, GPUs, FPGAs, and peripheral I/O chips, lacks the specialized fabrication processes possessed by other foundries. The success of acquiring Tower to expand its product line and market presence remains crucial.

Operational Segmentation: Apart from financial divisions, the division of physical facilities and actual production capacity must be strategically managed. Successfully emulating models like AMD/GlobalFoundries or Samsung LSI/Samsung Foundry, where there is a clear distinction between foundry and client, is essential. Simultaneously, Intel faces challenges in preventing orders from its significant client, the Intel Design Department, from flowing outward.

The official termination of the Tower acquisition plan introduces greater uncertainties and challenges for Intel in the competitive foundry market. In an industry marked by heightened competition, having dominance in specialized process technologies and diversified production lines is pivotal for sustaining profitability amid industry downturns. Without the assistance of Tower’s established specialized processes, Intel’s strategic approach and technology development in the foundry business will be worth monitoring.

(Photo credit: Intel)

As per a report from Taiwan’s TechNews,” TSMC, Samsung, and Intel have been actively deploying Backside Power Delivery Network (BSPDN) strategies recently, and have announced plans to incorporate BSPDN into their logic chip development roadmap. For instance, Samsung intends to implement BSPDN technology in its 2-nanometer chips, a move unveiled at the VLSI Symposium in Japan.

According to imec, BSPDN aims to alleviate the congestion issues faced by front-end logic chips in later-stage processes. Through Design Technology Co-Optimization (DTCO), more efficient wire designs are achieved in standard cells, aiding in the downsizing of logic standard cell.

In essence, BSPDN can be seen as a refinement of chiplet design. The conventional approach, where logic circuits and memory modules are integrated, is transformed into a configuration with logic functions on the front and power or signal delivery from the back.

While the traditional method of front-side wafer power delivery achieves its purpose, it leads to decreased power density and compromised performance. Nevertheless, the new BSPDN technique has not yet been adopted by foundries.

Samsung claims that, compared to the conventional method, BSPDN reduces area by 14.8%, providing more chip space for additional transistors and improved overall performance. Wire lengths are also cut by 9.2%, reducing resistance, allowing greater current flow, and thereby lowering power consumption while enhancing power transmission efficiency.

In June of this year, Intel also introduced its BSPDN-related innovations under the name ‘PowerVia.’ Team Blue plans to utilize this approach in the Intel 20A process, potentially achieving a chip utilization rate of 90%.

Intel believes PowerVia will address interconnect bottlenecks in silicon architecture, enabling continuous transmission through backside wafer powering. The company anticipates incorporating this novel approach into its Arrow Lake CPUs slated for release in 2024.

Furthermore, according to Taiwan’s supply chain sources, TSMC remains on track to launch its 2-nanometer process in 2025, with mass production expected in the latter half of the year in Hsinchu’s Baoshan. The company’s N2P process, planned for 2026, will feature BSPDN technology.

(Photo credit: Samsung)