Japanese telecommunications operator NTT is reportedly collaborating with American chipmaker Intel and other semiconductor manufacturers to research large-scale production of next-generation semiconductor technology, which involves significantly reducing power consumption using optical technology. ...

Intel announced on the evening of January 25th that it will collaborate with UMC to develop 12-nanometer process platform technology. The production will utilize Intel's wafer fab capacity in the United States, and both parties will share the cash generated from the collaboration. The production is ...

According to the report from TechNews, Intel CEO Pat Gelsinger, speaking at the World Economic Forum, stated that export sanctions from the United States, Japan, and the Netherlands are temporarily limiting China's development in semiconductor processes below 7 nanometers. Despite China's ongoing...

TSMC announced during its briefing on the 18th that, due to robust demand in the 2-nanometer market, it plans to add another fab to the initially planned two fabs in Kaohsiung. The company intends to use the 2-nanometer process for all three fabs in Kaohsiung, in addition to the originally planne...

The global foundry advanced process battle is reigniting, as reported by the Commercial Times. TSMC's 2-nanometer process at the Baoshan P1 wafer fab in Hsinchu is set to commence equipment installation as early as April, incorporating a new Gate-All-Around (GAA) transistor architecture and aiming f...