According to the news from Mydrivers.com, TSMC announced its ambitious plans for constructing cutting-edge 4nm and 3nm chip fabs in the United States. The move is expected to generate tens of thousands of job opportunities in the US job market. However, TSMC’s timeline for commencing production at its inaugural 4nm fab has been pushed back from 2024 to 2025. The attributed cause behind this delay is the insufficient availability of skilled American workers, causing setbacks in equipment installation.

This situation has led to a heated dispute between TSMC and local labor unions. TSMC’s assertion of a skilled worker deficit in the US has sparked disagreement from the unions. They assert that TSMC’s stance is a pretext for bringing in lower-wage overseas labor to vie for domestic employment opportunities. TSMC, on the other hand, refutes these claims, emphasizing that employing local staff on assignment doesn’t undermine their US-based operations or recruitment efforts.

Apart from the skill-related quandary, the delay in TSMC’s factory plans may have an underlying factor – the scorching conditions in Phoenix, Arizona. Sources report that the city has experienced an unbroken streak of over 20 days with temperatures hovering around 43 degrees Celsius. Notably, this heat wave has raised internal questioning within TSMC about the wisdom of selecting a desert-adjacent location for their facility.

According to this industry insider, the intense heat seemingly played a role in impeding progress. The sweltering climate of over 40 degrees Celsius undoubtedly hampers worker productivity, particularly for outdoor tasks.

The informer indicated that TSMC had an alternative option when choosing a location for its US facility. Aside from Arizona, they could have set up shop in Portland, the capital of Oregon, which is also a hub for the semiconductor industry. However, TSMC’s rationale for settling in Arizona remains undisclosed.

Notably, Phoenix, Arizona, is also a focal point for Intel’s chip investments, with the company injecting 20 billion USD into the establishment of new wafer fabs over the past couple of years.

(Source: https://news.mydrivers.com/1/928/928753.htm)

As semiconductor process technology nears known physical limits, the spotlight among major industry players is shifting towards the development of advanced packaging. Concurrently, the rise of applications like artificial intelligence and AIGC has propelled the concept of advanced packaging into a new technological wave. In the midst of the semiconductor industry’s global competition, securing more orders has become a core objective for major players.

A Competitive Landscape in Advanced Packaging

The competition in advanced packaging technology is intensifying, with companies pouring substantial investments into the field, resulting in a landscape of vigorous competition. Various packaging technologies have emerged, with notable offerings from industry giants such as TSMC, Intel, and Samsung.

TSMC introduced 3DFabric, an integration of its TSMC-SoIC front-end technology with CoWoS and InFO back-end technologies, providing maximum flexibility for diverse innovative product designs.

Intel, on the other hand, features its 2.5D EMIB and 3D Foveros packaging technologies. EMIB is applied in the connection of logic chips and high-bandwidth memory, as seen in the Intel Xeon Max series and Intel Data Center GPU Max series.

Foveros allows top dies to overcome size limitations and accommodate more top and base dies, connected through copper pillars to reduce potential interference from through-silicon vias (TSVs).

Samsung also exhibits strong competitiveness in advanced packaging, with its 2.5D I-Cube4 and H-Cube, along with 3D X-Cube packaging technologies, achieving breakthroughs in multi-chip interconnects and integration.

Samsung’s I-Cube4, for example, integrates four HBM stack dies and one core compute IC on the silicon interposer layer, while H-Cube enhances packaging area through the stacking of HDI PCBs to accommodate designs with six or more HBM stack dies.

Advantages of the Three Giants

In recent years, the three semiconductor giants have directed substantial capital expenditure towards advanced packaging. Their diverse technological developments and marketing strategies are poised to ignite a global battle in the semiconductor advanced packaging industry.

TSMC holds the advantage with its dominant wafer process technology and an end-to-end comprehensive service approach. Coupled with Taiwan’s robust semiconductor ecosystem, TSMC leads the way in the advanced packaging domain.

Intel, while slightly trailing TSMC in advanced process technology, matches it in advanced packaging capabilities. Emphasizing flexible foundry services, Intel allows clients to mix and match its wafer manufacturing and packaging offerings. With manufacturing facilities scattered worldwide, Intel leverages geographic advantages, particularly in Western countries, to expand capacity and services, leading to anticipated gains in the future.

Samsung, like TSMC, offers end-to-end services, but its packaging technology lags behind TSMC’s. It secures a share in constrained supply situations. Notably, Samsung, in June 2022, was ahead of TSMC in unveiling the innovative GAA 3nm process, and is poised to combine it with 3D packaging technology, potentially marking a pivotal point in the next semiconductor generation.

With semiconductor technology’s continuous evolution and surging market demand, the competition among the three giants in advanced packaging will remain fierce. While wafer fabs currently prioritize processes, the next three to five years are expected to witness a gradual shift towards advanced packaging. Different packaging technologies and marketing strategies will ultimately determine companies’ positions and influence in the market.

(Photo credit: TSMC)

Read more:

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• ASE, Amkor, UMC and Samsung Getting a Slice of the CoWoS Market from AI Chips, Challenging TSMC

Leading semiconductor companies are making significant strides in global expansion with the announcement of two new fabrication facilities. TSMC is set to greenlight a factory in Germany, while GlobalFoundries plans to establish its first 12-inch wafer plant in Singapore.

TSMC’s Bold Move: Germany’s Green Light

TSMC from its presence in the USA, China (Shanghai and Nanjing), to Japan (Kumamoto City), TSMC’s global manufacturing footprint is expanding. Reuters reported on August 7 that TSMC’s board is inclined to approve the construction of a plant in Dresden, Germany. The German government pledges a substantial 5 billion euros (about $5.49 billion USD) to support the facility. However, the German Ministry of Economy refrains from commenting on the matter.

TSMC has been negotiating with the Saxony German state since 2021 to establish a collaborative FAB plant. In partnership with Bosch, Infineon, and Onsemi, TSMC aims to utilize the Dresden plant primarily for automotive chip production. Pending board approval, this venture could involve financing discussions with Berlin, ultimately requiring European Commission endorsement. TSMC, Intel, and Wolfspeed stand out among chip manufacturers seeking government assistance for European manufacturing ventures.

GlobalFoundries Poised to Build 12-Inch Wafer Plant in Singapore

According to udn.com, GlobalFoundries is set to make a substantial investment in the establishment of a 12-inch wafer fabrication plant in Singapore. The project’s funding could exceed NT$100 billion (approximately $3.2 billion USD). Reports suggest that this Singaporean facility will focus on producing 28-nanometer chips, with a potential completion date as early as 2026.

Industry experts note that GlobalFoundries’ move to set up a 12-inch facility in Singapore implies a significant shift in the competitive landscape. TSMC, UMC, PSMC, and GlobalFoundries – the four major semiconductor foundries – will all possess 12-inch production capabilities. Additionally, each of these companies has international expansion plans for such facilities. Notably, TSMC’s ventures span across the USA and Japan, UMC, and GlobalFoundries are both targeting Singapore, while PSMC’s strategy involves establishing a plant in Japan in collaboration with local partners.

Major Manufacturers Expand Against the Current Downturn

TSMC has been proactive in its expansion strategy, unveiling plans for ten new facilities in the past two years. These include 5 wafer plants and 2 advanced packaging facilities in Taiwan, alongside 3 overseas wafer plants. Despite the industry’s current challenges, TSMC’s expansion momentum remains strong, driven by a heightened focus on global manufacturing diversity.

TSMC is well aware of the potential risks tied to significant expansion efforts. In its latest annual report, the company acknowledges that expanding on a global scale demands substantial resources, highlighting possible challenges like rising costs, workforce shortages, disasters, land scarcity, cyber threats, government support, cultural differences, intellectual property protection, and tax variations.

Expanding during a semiconductor downturn has become a strategic approach for the foundry players. Typically, a fab construction takes 2 to 4 years, with equipment installation lasting 0.5 to 1 year and production ramp-up stretching 1 to 2 years. Looking ahead, semiconductor foundries are gearing up for a fresh wave of capacity release throughout 2024 and 2025.

Despite the industry’s ongoing slump, encouraging signs suggest that the downturn might be reaching its conclusion. Industry experts are cautiously optimistic, anticipating the arrival of the next upswing in the cycle.

(Source: https://mp.weixin.qq.com/s/4Xu_uc58kG85E_6R4Y3qhQ)

According to the latest report from TrendForce, the primary factors influencing the global market share of notebook CPUs in 2024 can be categorized into “Architectural Design” and “Economic Factors.”

“Architectural Design” as a long-term factor affecting market share:

(1) Both AMD (AMD 3D V-Cache) and Intel (Intel Foveros Direct) may potentially integrate 3D packaging technology into notebook computers in the future.

(2) Apple’s M-series processors, using the Arm core architecture, as well as Intel processors, have adopted a big/little core hybrid design. AMD might also introduce this in the Ryzen 8000 series.

(3) Despite further advancements in processor technology by 2024, the notebook computer market remains highly sensitive to the cost for IT equipment.

“Economic Factors” as more immediate influencers of market share:

(1) Until 2024, a return to lower interest rates in the global economic environment could favor corporate expansion of capital expenditure. This could result in increased procurement of business-oriented notebook models, potentially allowing Intel to further expand its CPU market share beyond 70% in the business sector.

(2) Concerns about economic prospects among global citizens until 2024 could have significant negative implications for the consumer notebook computer market. With the restart of physical economic activities, the demand for consumer-oriented notebook models has declined from the high levels seen during the pandemic. Consequently, the consumer market demand outlook for 2024 remains uncertain. For AMD, which relies more on consumer market demand, changes in market share may be harder to predict compared to Intel.

In the post-pandemic era, AMD, Arm/Apple, and Intel are pursuing distinct technological competition strategies to capture market share in the personal computing market.

AMD:

(1) The Socket AM5 platform is poised to aid AMD CPUs in achieving substantial performance and efficiency gains.

(2) The AMD Ryzen 7040 incorporates an artificial intelligence engine to emphasize AI computing performance’s importance in the thin and light notebook market.

Arm/Apple:

(1) The M2 Ultra processor heralds Apple’s complete transition of personal computing products to the Arm core. Apple Mac computer products will no longer be sold with Intel processor.

(2) The Apple M-series processors, built on the Arm core architecture, facilitate a “fanless design” to maintain MacBook’s slim profile. This feature highlights its irreplaceable positioning in the portable notebook computer market, emphasizing portability.

Intel:

(1) With the waning trend of the “hybrid work mode,” Intel is optimistic about diversified development in the post-pandemic era for desktop computer products. This includes microcomputers, micro workstations, and general workstations. Due to the characteristic of continuous operation for 24 hours, desktop computers still possess unique attributes that cannot be replaced by notebook computers.

(Photo credit: Intel)

With the advancements in AIGC models such as ChatGPT and Midjourney, we are witnessing the rise of more super-sized language models, opening up new possibilities for High-Performance Computing (HPC) platforms.

According to TrendForce, by 2025, the global demand for computational resources in the AIGC industry – assuming 5 super-sized AIGC products equivalent to ChatGPT, 25 medium-sized AIGC products equivalent to Midjourney, and 80 small-sized AIGC products – would be approximately equivalent to 145,600 – 233,700 units of NVIDIA A100 GPUs. This highlights the significant impact of AIGC on computational requirements.

Additionally, the rapid development of supercomputing, 8K video streaming, and AR/VR will also lead to an increased workload on cloud computing systems. This calls for highly efficient computing platforms that can handle parallel processing of vast amounts of data.
However, a critical concern is whether hardware advancements can keep pace with the demands of these emerging applications.

HBM: The Fast Lane to High-Performance Computing

While the performance of core computing components like CPUs, GPUs, and ASICs has improved due to semiconductor advancements, their overall efficiency can be hindered by the limited bandwidth of DDR SDRAM.

For example, from 2014 to 2020, CPU performance increased over threefold, while DDR SDRAM bandwidth only doubled. Additionally, the pursuit of higher transmission performance through technologies like DDR5 or future DDR6 increases power consumption, posing long-term impacts on computing systems’ efficiency.

Recognizing this challenge, major chip manufacturers quickly turned their attention to new solutions. In 2013, AMD and SK Hynix made separate debuts with their pioneering products featuring High Bandwidth Memory (HBM), a revolutionary technology that allows for stacking on GPUs and effectively replacing GDDR SDRAM. It was recognized as an industry standard by JEDEC the same year.

In 2015, AMD introduced Fiji, the first high-end consumer GPU with integrated HBM, followed by NVIDIA’s release of P100, the first AI server GPU with HBM in 2016, marking the beginning of a new era for server GPU’s integration with HBM.

HBM’s rise as the mainstream technology sought after by key players can be attributed to its exceptional bandwidth and lower power consumption when compared to DDR SDRAM. For example, HBM3 delivers 15 times the bandwidth of DDR5 and can further increase the total bandwidth by adding more stacked dies. Additionally, at system level, HBM can effectively manage power consumption by replacing a portion of GDDR SDRAM or DDR SDRAM.

As computing power demands increase, HBM’s exceptional transmission efficiency unlocks the full potential of core computing components. Integrating HBM into server GPUs has become a prominent trend, propelling the global HBM market to grow at a compound annual rate of 40-45% from 2023 to 2025, according to TrendForce.

The Crucial Role of 2.5D Packaging

In the midst of this trend, the crucial role of 2.5D packaging technology in enabling such integration cannot be overlooked.

TSMC has been laying the groundwork for 2.5D packaging technology with CoWoS (Chip on Wafer on Substrate) since 2011. This technology enables the integration of logic chips on the same silicon interposer. The third-generation CoWoS technology, introduced in 2016, allowed the integration of logic chips with HBM and was adopted by NVIDIA for its P100 GPU.

With development in CoWoS technology, the interposer area has expanded, accommodating more stacked HBM dies. The 5th-generation CoWoS, launched in 2021, can integrate 8 HBM stacks and 2 core computing components. The upcoming 6th-generation CoWoS, expected in 2023, will support up to 12 HBM stacks, meeting the requirements of HBM3.

TSMC’s CoWoS platform has become the foundation for high-performance computing platforms. While other semiconductor leaders like Samsung, Intel, and ASE are also venturing into 2.5D packaging technology with HBM integration, we think TSMC is poised to be the biggest winner in this emerging field, considering its technological expertise, production capacity, and order capabilities.

In conclusion, the remarkable transmission efficiency of HBM, facilitated by the advancements in 2.5D packaging technologies, creates an exciting prospect for the seamless convergence of these innovations. The future holds immense potential for enhanced computing experiences.