On August 8th, Japan experienced a magnitude 7.1 earthquake with the epicenter located off the coast of Kyushu, in the sea east of Miyazaki Prefecture, at a focal depth of 30 kilometers. TSMC’s Kumamoto plant (JASM), located in Kumamoto Prefecture, experienced a seismic intensity scale of level 4.

As per a report from Commercial Times, regarding the impact of the earthquake, TSMC stated that the seismic intensity scale at the Kumamoto plant did not reach the evacuation threshold and is not expected to impact operations.

The schedule for its Kumamoto fab to start mass production in the fourth quarter remains unaffected, and construction work on the second plant has already begun. Kumamoto Prefecture Governor Takashi Kimura is scheduled to visit Taiwan at the end of August to actively seek a third plant.

TSMC’s first JASM plant in Kumamoto is set to start mass production in the fourth quarter, focusing on 12nm and 16nm processes. Construction work on the site for the second plant began at the end of the second quarter, with the building scheduled to break ground in the second half of the year.

Notably, Takashi Kimura, who took office in April, stated in an report from Bloomberg on May 11th that he would spare no effort to persuade TSMC to establish a third fab in the region, believing that during the preparations for TSMC’s first fab in Kumamoto, the region already possesses better-quality road and water infrastructure and an education system that better supports international school students, which could be advantageous.

Kyushu is a key region for Taiwan’s semiconductor industry. Recently, ASE Group, a leading packaging and testing company, decided to purchase land and establish a plant in Kitakyushu.

Testing company MA-tek, semiconductor materials distributor Topco Scientific, and Gudeng Precision have all set up bases in Kumamoto, while Gudeng is also planning to establish a new plant in Kurume, between Fukuoka and Kumamoto.

TSMC has indicated that most of its production sites, suppliers, customers, and upstream suppliers of semiconductor manufacturing services are located in areas susceptible to natural disasters.

Thus, to mitigate the risks that could lead to operational disruptions, TSMC has reportedly strengthened its ability to effectively respond to these risks through business continuity management to ensure operational resilience across its supply chain.

Commercial Times reported that from the very beginning of construction, TSMC has been reinforcing building structures, facilities, and equipment, along with implementing preventive measures. This is done to ensure that the plant remains undamaged, with no chemical leaks, equipment displacement, or injuries to personnel.

The evacuation standards for JASM are consistent with those of TSMC’s other plants in Taiwan. The recent earthquake did not meet the threshold for evacuation, so it is not expected to impact operations. This event also served as a stress test before mass production begins, the report noted.

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• [News] TSMC’s Kumamoto Fab 2 Reportedly Begins Land Preparation
• [News] Kumamoto Vying for TSMC’s Third Fab, Looking to Build Semiconductor Hub

(Photo credit: TSMC)

According to a report from Nikkei on August 5, RS Technologies, a global giant in recycled wafers, has announced that due to increased orders, it will expand the monthly production capacity of its Japanese and Taiwanese plants to 580,000 wafers by 2024.

Despite the Japanese plant operating at full capacity, the company is still unable to meet the surging demand, prompting it to implement new investment plans to further increase production.

RS Technologies President Fang Yong Yi explained that there are various processes in semiconductor manufacturing, and many of them require repeated quality checks and testing, which utilize reclaimed wafers.

These reclaimed wafers are cleaned and subjected to precise regeneration processes, with each wafer being recyclable about 10 times. The company estimates that global monthly production output of reclaimed wafers will increase by 32% from 1.32 million in 2023 to 1.74 million in 2024.

Regarding TSMC’s new plant in Kumamoto Prefecture, which hints at a resurgence in semiconductor production within Japan, Fang noted that in 2023, orders for reclaimed wafers from major Japanese semiconductor companies like Kioxia significantly declined. However, in 2024, orders are expected to increase by 10,000 to 20,000 wafers month by month.

For 2024, the combined monthly production of RS Technologies’ Japanese and Taiwanese plants is projected to rise from 540,000 in 2023 to 580,000.

Reportedly, the Japanese plant is currently operating at full capacity with a 24-hour, three-shift system but still cannot meet demand. The plant’s current monthly production is 320,000 wafers, and new equipment investments are planned to add 170,000 wafers to the monthly capacity soon.

Fang further noted that orders for recycled test wafers from overseas vendors have also increased. New plants require a large volume of test wafers, and thus the simultaneous construction of new plants by overseas manufacturers represents a significant opportunity for the company.

RS Technologies, in a financial report released on May 13, announced plans to expand its overall monthly production capacity of reclaimed wafers to over 890,000 units by the end of 2026 to meet strong demand.

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• [News] Japan’s “Silicon Island” Reawakening? Taiwanese Semiconductor Companies Follow TSMC to Kyushu
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According to STDaily citing a recent report on the official website of Okinawa Institute of Science and Technology Graduate University (OIST) in Japan announced that, the university has designed an extreme ultraviolet (EUV) lithography technology that surpasses the standard boundary of semiconductor manufacturing.

Lithography equipment based on such a design can use a smaller EUV light source, consuming less than one-tenth the power of traditional EUV lithography equipment, which can reduce costs and significantly improve the reliability and lifespan of the equipment.

In traditional optical systems, such as camera, telescope, and conventional ultraviolet lithography technologies, optical elements like apertures and lenses are arranged symmetrically along a straight axis. This method is not suitable for EUV rays because their wavelengths are extremely short and most will be absorbed by materials.

Thus, EUV light is guided using crescent-shaped mirrors, but this leads to light deviation from the central axis, sacrificing important optical properties and reducing the overall performance of the system.

To tackle this issue, the new lithography technology achieves its optical properties by aligning two axisymmetric mirrors with tiny central holes in a straight line. Due to the high absorption rate of EUV, each mirror reflection weakens the energy by 40%.

In accordance with industry standards, only about 1% of the EUV light source energy reaches the wafer after passing through 10 mirrors, which requires a very high EUV light output.

In contrast, limiting the number of mirrors from the EUV light source to the wafer to a total of four allows more than 10% of the energy to penetrate the wafer, which can largely bring down power consumption.

The core projector of the new EUV lithography technology, consisting of two mirrors similar to an astronomical telescope, can transfer the light mask image onto the silicon wafer. The team claims this configuration is incredibly simple since traditional projectors require at least six mirrors.

This was achieved by rethinking the theory of optical aberration calibration, and its performance has been verified by optical simulation software, which means it can meet the production requirements of advanced semiconductors.

Besides, the team designed a new type of illumination optical method called “dual-line field” for this novel technology, which uses EUV light to illuminate a plane mirror light mask from the front without interfering with the light path.

Read more

• [News] TSMC Reveals High-NA EUV Equipment Will Be Adopted at the Right Time
• [News] Price for ASML’s Hyper-NA EUV Rumored to Double, Causing TSMC, Samsung and Intel to Hesitate

(Photo credit: OIST)

According to a report by the Commercial Times, while TSMC, the global foundry leader, has established a plant in Kikuyo, Kumamoto City, Kyushu. ASE Technology Holdings (ASE), a giant in packaging industry, is setting up a plant in Kitakyushu as well. With these developments, Japan’s semiconductor production could potentially integrate both front-end and back-end processes, forming a cluster within Kyushu.

This development could lead to a revival of Kyushu’s semiconductor industry, once known as the “Silicon Island” in Japan, attracting more semiconductor supply chain companies to the region.

The report further notes that related equipment and inspection company, including MA-tek, semiconductor transmission and storage solutions provider Gudeng Precision, and semiconductor material distributor Topco Technologies Corp. (Topco) have all established bases in Kumamoto.

MA-tek, a leader in semiconductor inspection and analysis services, established its first Japanese laboratory in 2019 and a second one in Kumamoto in 2023. Since their establishment, these laboratories have consistently achieved growth rates higher than the company average.

With the rise of AI applications, many Japanese clients have AI chip development projects, leading to increased demand for MA-tek’s materials analysis (MA) and advanced process inspection services.

To capitalize on advanced process and packaging opportunities brought by AI, the company MAT has decided to increase its capital expenditure this year to between NTD 1.2 billion and NTD 1.4 billion.

These funds will be used to expand and upgrade the testing equipment and laboratory facilities in Nagoya and Kumamoto, and to establish a third laboratory in Hokkaido, which is expected to start contributing to revenue in Q1 2025.

On the other hand, Gudeng Precision is also planning to build a new plant in Kurume in Q2 this year, located between Fukuoka and Kumamoto, with a planned area of approximately 3,000 ping (about 10,000 square meters).

Gudeng Precision’s investment in Kurume, Japan, including equipment procurement, is estimated at about NTD 400 million to NTD 450 million. Construction is expected to begin by the end of this year, with production slated to start by the end of 2025.

Read more

• [News] TSMC’s JASM Kumamoto Plant 2 Greenlit, Construction Expected to Commence by Year’s End
• [News] Kumamoto Vying for TSMC’s Third Fab, Looking to Build Semiconductor Hub

(Photo credit: JASM)

According to a report from Nikkei, Japanese government is considering introducing a certain bill to provide guaranteed loans to the government-backed chip startup Rapidus. This measure is expected to help the company attract private investment and reduce its reliance on government subsidies.

Rapidus is reportedly building a plant in Chitose, Hokkaido, with the goal of mass-producing 2-nanometer chips by 2027. Before reaching this milestone, the company may need between JPY 3 trillion and 4 trillion (approximately USD 19 billion to 25 billion) in funding.

Yoshihiro Seki, one of the senior Japanese Liberal Democratic Party (LDP) figures on semiconductor policies, stated that most of this funding would likely come from bank loans, but he acknowledged that seeking loans without any output from Rapidus could deter financial institutions.

Established in August 2022, Rapidus was jointly founded by eight Japanese companies, including Toyota, Sony, NTT, NEC, Softbank, Denso, Kioxia (formerly Toshiba Memory Corporation), and Mitsubishi UFJ, which have collectively invested JPY 7.3 billion per Nikkei. However, this amount is still far short of the funds needed for mass production. 

The Japanese government has pledged to inject JPY 1 trillion into Rapidus. However, Yoshihiro Seki remarked that given Japan’s fiscal situation, it is indeed quite difficult to provide several trillion yen in funding to Rapidus annually. He hopes Rapidus can adapt to the trend and quickly become self-reliant, without depending on government financial aid.

Japanese Prime Minister Fumio Kishida recently visited Rapidus’s plant in Hokkaido and stated that the government would promptly submit a bill to the National Diet to support Rapidus in mass-producing the next generation of semiconductors. Seki revealed that the Japanese government is expected to submit the bill before the autumn session of the Diet.

Japanese law prohibits the government from providing guaranteed loans to specific companies unless the funding benefits the public. In the past, the Japanese government provided loans to Tokyo Electric Power Company (TEPCO) to compensate victims of the Fukushima nuclear disaster.

Some sources cited in Nikkei’s report question Rapidus’ competitiveness and the extent of government aid, as the company’s timeline for producing 2-nanometer chips lags behind major competitors like TSMC and Samsung Electronics by two years. Despite this, Yoshihiro Seki remains confident in Rapidus’s potential for success, citing the anticipated rapid growth of AI applications as one reason for optimism.

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• [News] Rapidus Partners RISC-V Player Esperanto, Targeting Low-Power AI Chip
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(Photo credit: Rapidus)