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Japanese NAND Flash giant Kioxia is striving for a V-shaped recovery in its performance. According to a report from Japanese news outlet 47news, benefiting from the quick rebound in the semiconductor market, Kioxia’s revenue this fiscal year is reportedly set to reach an all-time high, with operating profit nearing a historic second-highest level.
It is reported that Kioxia’s revenue for the fiscal year 2024 (April 2024 – March 2025) is estimated to reach JPY 1.6 trillion, setting a new historical high.
This is expected to be accompanied by an operating profit of around JPY 300 billion. Kioxia’s strong performance this fiscal year is in contrast with the previous fiscal year (April 2023 – March 2024), which recorded a loss of JPY 252.7 billion, the largest in its history.
The report also suggests that Kioxia is forecasted to maintain similar strong performance in the next fiscal year 2025 (April 2025 – March 2026).
The company’s highest annual revenue record stands at JPY 1.5265 trillion for the fiscal year 2021, with a peak operating profit of JPY 456.8 billion in the fiscal year 2017.
Kioxia was formerly known as Toshiba Memory. It became an independent entity spun off from Toshiba in June 2018 and rebranded as Kioxia in October 2019.
Recently, Japanese news outlet Nikkei reported that Kioxia submitted its listing application to the Tokyo Stock Exchange on August 23, with the goal of going public as soon as October.
Reportedly, Kioxia’s valuation is expected to exceed JPY 1.5 trillion (roughly USD 10.3 billion). The deal is anticipated to surpass the JPY 420 billion raised by chip equipment maker Kokusai Electric during its 2023 IPO, which was the largest of that year.
It is also expected to exceed the projected listing of Tokyo Metro in October, estimated at JPY 640 billion to 700 billion.
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(Photo credit: Kioxia)
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Kioxia has moved forward with its plans to go public, starting the process on August 23. This development follows Bain Capital, a U.S. private equity firm with a majority stake in Kioxia, submitting an application for the listing to the Tokyo Stock Exchange on the same day, according to Nikkei.
Kioxia, formerly Toshiba Memory Corporation, was spun off from Toshiba in 2018 and rebranded. Bain Capital spearheads a special purpose company that, along with South Korea’s SK Hynix, holds a 56% stake in Kioxia Holdings, making it the largest shareholder. Toshiba retains a 41% stake.
SK Hynix first invested in Kioxia in 2018, committing a total of 4 trillion won (around $2.9 billion). This investment was split between 2.7 trillion won into a private equity fund led by Bain Capital and 1.3 trillion won to acquire Kioxia convertible bonds issued by Toshiba. However, the latest report from Korean media BusinessKorea highlights that SK Hynix has faced difficulties recovering its investment due to Kioxia’s delayed IPO, failed merger attempts, and a weak semiconductor market.
Kioxia had planned to list on the Tokyo Stock Exchange in 2020, but escalating trade tensions between the U.S. and China led to a postponement. In 2023, Kioxia attempted to merge with Western Digital’s memory division to better compete with Samsung Electronics in the NAND flash market, but the effort was blocked by SK Hynix.
Despite these challenges, Kioxia posted a net profit of 69.8 billion yen in the second quarter of this year, its highest second-quarter earnings, as demand for memory in smartphones and PCs bottomed out. With signs of a semiconductor market recovery, Kioxia is pushing for a re-listing to enhance its financial flexibility.
According to Nikkei, after the listing, Bain Capital and Toshiba are expected to gradually reduce their stakes through share sales. SK hynix is also likely to sell part of its stake to recover its investment while maintaining strategic ties with Kioxia and Toshiba.
BusinessKorea believes that should Kioxia achieve a high valuation and successfully go public later this year, SK Group could recover its investment, enabling SK Hynix to reinvest in high-bandwidth memory (HBM) for AI applications.
(Photo credit: Kioxia)
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According to a report by the Nikkei, Japanese chip manufacturer Kioxia has submitted its initial public offering (IPO) application to the Tokyo Stock Exchange, triggering a long-awaited move as the development of artificial intelligence (AI) drives a surge in semiconductor demand. The company aims to go public in October, the report notes.
According to a report by Nikkei, citing sources, Kioxia’s valuation is expected to exceed JPY 1.5 trillion (roughly USD 10.3 billion). The deal is anticipated to surpass the JPY 420 billion raised by chip equipment maker Kokusai Electric during its 2023 IPO, which was the largest of that year. It is also expected to exceed the projected listing of Tokyo Metro in October, estimated at JPY 640 billion to 700 billion.
This move comes at a time when the Japanese government is increasing its support for investment in the chip industry, aiming to secure the supply of critical components amid rising geopolitical tensions.
As per another report from Anue, Kioxia had once planned to conduct its IPO in 2020.
However, the plan was postponed due to the uncertainty in the global chip market caused by U.S.-China trade tensions and the outbreak of the COVID-19 pandemic. At that time, Kioxia’s target valuation exceeded 2 trillion yen, which was later reduced to 1.7 trillion yen.
Last year, Kioxia engaged in merger talks with Western Digital’s flash memory business, but the negotiations stalled due to opposition from Kioxia’s shareholder, SK hynix.
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(Photo credit: Kioxia)
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As per a report from Kyodo News on August 21st, that the Japan-based chip manufacturer Rapidus is expected to begin mass production of 2nm chips by 2027. To secure the necessary funds for semiconductor production, Rapidus is reportedly seeking JPY 100 billion in financing from banks.
Reportedly, Rapidus has requested financing from Japan’s three major banks—Mitsubishi UFJ Financial Group, Sumitomo Mitsui Banking Corporation, and Mizuho Bank—as well as from the Development Bank of Japan.
Additionally, Rapidus has asked existing shareholders, including Toyota, for additional investment. The response of these shareholders is now a key point of interest.
Rapidus, established in August 2022, is a joint venture funded by eight Japanese companies: Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND Flash maker Kioxia, and Mitsubishi UFJ.
The report further indicates that Rapidus currently relies mainly on government subsidies to advance its projects. To achieve its goal of mass-producing 2nm chips by 2027, a total investment of approximately JPY 5 trillion from both public and private sectors is expected.
If Rapidus secures the requested 100 billion yen in financing, it would mark the first major funding from financial institutions, representing a significant step forward for the company.
Per an earlier report from Nikkei, the Japanese government has so far decided to provide JPY 920 billion in subsidies to Rapidus. Additionally, the eight private Japanese companies, including Toyota, have invested JPY 7.3 billion in the venture.
However, there remains a funding gap of about JPY 4 trillion. Establishing production technology and acquiring customers are challenging tasks, and some banks are cautious about providing financing, which may pose obstacles to meeting the funding requirements.
Nikkei’s report on August 10 also pointed out that Rapidus, which began construction on its 2nm wafer fab in Hokkaido last September, plans to start mass production of 2nm chips by 2027.
The external construction of the facility is expected to be completed in October this year, with the installation of Japan’s first extreme ultraviolet (EUV) lithography equipment scheduled for December. The plan includes introducing several additional EUV machines in the future.
Koike expressed confidence in achieving the 2027 mass production goal and emphasized that Rapidus aims to produce semiconductors at least twice as fast as its competitors, with potential speed increases for smaller batches.
He also addressed that the company will collaborate with Japan’s top material and equipment suppliers to lower costs and produce globally competitive products.
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(Photo credit: Rapidus)
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As the battle of HBM intensifies between memory giants, the competition of NAND is also heating up. According to a report by Korean media outlet etnews, SK hynix is developing 400-layer NAND flash memory, aiming to get the technology ready for mass production by the end of 2025.
Citing sources familiar with the matter, the report notes that SK hynix is currently working with supply chain partners to develop process technologies and equipment needed for 400-layer and above NANDs. As the company plans to apply hybrid bonding to achieve the breakthrough, many packaging materials and components suppliers are expected to enter the new supply chain.
According to the report, SK hynix is reviewing new materials for bonding and various technologies for connecting different wafers, including polishing, etching, deposition, and wiring. With the goal of getting the technology and infrastructure ready by the end of next year, full-scale production for the 400-layer NAND is anticipated to begin in the first half of 2026.
Currently, the Big Three in the memory sector are all trying to push the boundaries on the layers of NAND. Earlier in April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), with the number of layers reaching 290. For now, the company aims to stack V-NAND to over 1000 layers by 2030.
Micron, on the other hand, has announced the 2650 client SSD, its first product built from 276-layer 3D NAND on July 30th. Japanese memory chipmaker Kioxia, after successfully increasing the number of 3D NAND layers to 218 in 2023, even stated that achieving a 1,000-layer level by 2027 would be possible.
In August, 2023, SK hynix showcased its sample of the world’s first 321-layer NAND product. Now, as the limit is expected to be pushed up to 400 layers, the company plans to apply hybrid bonding to the manufacturing, which adopts a “wafer-to-wafer” (W2W) structure, etnews notes.
According to the report, until now, SK hynix has been stacking cells on top of the peripherals, the driving circuit area, using the method of “Peripheral Under Cell (PUC)” to manufacture NAND. The structure is similar to a mixed-use high-rise apartment where the peripheral (commercial space) is at the bottom and the cells (residential units) are stacked on top.
However, as the number of NAND layers increases, the peripheral is prone to be damaged during the cell stacking process due to the high heat and pressure generated during the cell process, the report explains.
Therefore, SK hynix plans to apply hybrid bonding to overcome the issues. By implementing cells and peripherals on separate wafers and then bonding the two wafers together, the method allows the peripheral wafer that drive the cells to be separately manufactured, thus enabling a stable increase in NAND layers.
Regarding the progress on the development of 400-layer NAND, SK hynix stated that it cannot confirm details about its technology development or mass production timeline, the report notes.
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(Photo credit: SK hynix)