Taiwan’s semiconductor giant, TSMC, faces overwhelming demand for its 3nm technology, with major clients like Apple and NVIDIA fully allocate its production capacity.

According to a report from Commercial Times, orders are expected to be filled through 2026. Reportedly, TSMC is planning to raise its 3nm prices by over 5%, and advanced packaging prices are anticipated to increase by approximately 10% to 20% next year.

The members of TSMC’s 3nm family include N3, N3E, N3P, as well as N3X and N3A. As the existing N3 technology continues to be upgraded, N3E, which began mass production in the fourth quarter of last year, targets applications such as AI accelerators, high-end smartphones, and data centers.

N3P is scheduled for mass production in the second half of this year and is expected to become mainstream for applications in mobile devices, consumer products, base stations, and networking through 2026. N3X and N3A are customized for high-performance computing and automotive clients.

Source: TSMC

Per the industry sources cited by the same report, TSMC’s Zhunan advanced packaging plant (AP6), operational for a year now, has become Taiwan’s largest CoWoS base with the equipment moved into its AP6C plant. In the third quarter, CoWoS monthly production capacity is expected to double from 17,000 to 33,000 wafers.

Industry sources cited by the report further suggests that while AI accelerators do not use the most cutting-edge manufacturing processes, they rely heavily on advanced packaging technology. The ability of global semiconductor companies to secure more advanced packaging capacity from TSMC will determine their market penetration and control.

TSMC’s advanced packaging capacity is scarce, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. Broadcom, Amazon, and Marvell have also expressed strong interest in using advanced packaging processes. With gross margins close to 80%, NVIDIA is said to agree to price increases to secure more advanced packaging capacity, thereby distancing itself from competitors.

Previously, NVIDIA CEO Jensen Huang emphasized that TSMC is not just manufacturing wafers but also handling numerous supply chain issues. He also agreed that the current pricing is too low and would support TSMC’s price increase actions.

The industry sources cited by Commercial Times have indicated that TSMC plans to add CoWoS-related equipment by the third quarter and has requested equipment manufacturers to dispatch more engineers to fully staff its Longtan AP3, Zhunan AP6, and Central Taiwan Science Park AP5 plants.

In addition to Zhunan’s AP6C, the Central Taiwan Science Park plant, which originally only handled the latter stages of oS, will also gradually transition to CoW processes. Meanwhile, the Chiayi site is in the land preparation stage and is expected to progress faster than Tongluo.

Reportedly, industry sources further reveal that the prices for advanced process nodes such as 3nm and 5nm will also be adjusted. Particularly, strong demand for 3nm orders in the second half of the year is expected to drive utilization rates to near full capacity, extending through 2025. The 5nm process is experiencing similar demand dynamics, driven by AI needs.

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] NVIDIA CEO Jensen Huang Supports C.C. Wei’s Theory and Backs for TSMC to Increase Price

(Photo credit: TSMC)

Driven by AI-driven demand for optical communication and ASICs, Marvell, a major network IC design company, is accelerating its AI-related business. According to a report from Commercial Times, the revenue from this segment is expected to grow from USD 200 million in fiscal year 2023 to USD 550 million in fiscal year 2024.

Marvell previously announced plans to utilize TSMC’s process technology to produce a 2-nanometer chip optimized for accelerating infrastructure. Reports suggest that TSMC will be a primary beneficiary of Marvell’s chip fabrication business.

“The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure capable of delivering on the promise of AI. Our partnership with TSMC on our 5nm, 3nm and now 2nm platforms has been instrumental in helping Marvell expand the boundaries of what can be achieved in silicon,” said Sandeep Bharathi, chief development officer at Marvell, in Marvell’s previous press release.

In addition, Marvell holds a high market share in the global optical communication digital signal processor (DSP) field. Marvell pointed out that AI has accelerated the rate of transmission speed upgrades, reducing the doubling cycle from 4 years to 2 years, thereby driving rapid growth in the company’s performance.

During Marvell AI Day, company management expressed optimism about its AI business outlook and shared the positive news of receiving AI chip orders from large technology companies. At the time, industry sources have speculated that this customer could be Microsoft.

Marvell CEO Matt Murphy revealed that the company has acquired its third AI hyperscale customer and is developing an AI accelerator slated for production in 2026. These orders encompass customized AI training accelerators and AI inference accelerators for Customer A, a customized Arm architecture CPU for Customer B, and a new customized AI accelerator for Customer C.

Marvell indicates that the AI training accelerators for Customer A and the Arm architecture CPU for Customer B are currently in the ramp-up phase for production. The AI inference accelerator for Customer A and the AI accelerator for Customer C are scheduled for production in 2025 and 2026, respectively.

The report cites sources indicating that Marvell’s customer B is Google, and the Arm-based CPU in question is the recently unveiled Google Axion. However, Marvell has not responded to this information.

Marvell highlighted advancements in chip technology, including advanced packaging techniques that integrate multiple chips.

Read more

• [News] The Imminent Arrival of 2-Nanometer Advanced Process
• [News]The 2nm Semiconductor Foundry Race Between TSMC, Samsung, Rapidus Begins with an Equipment Battle

(Photo credit: TSMC)

Recently, IC design company Marvell announced an expansion of its long-term partnership with TSMC to include 2-nanometer technology. They will collaborate on developing the industry’s first 2-nanometer semiconductor production platform optimized for accelerating infrastructure.

Currently, the most advanced production technology in the industry is the 3-nanometer process, manufactured by Samsung Electronics and TSMC. With Intel securing the first ASML lithography machine and updating its latest manufacturing roadmap, and with the increasing collaboration between Rapidus and IBM, the competition for the 2-nanometer advanced process has significantly expanded to include TSMC, Intel, Samsung and  Rapidus.

• Marvell

According to Marvell’s press release, it has stated that Marvell has transitioned from a follower to a leader in integrating advanced node technology into silicon infrastructure.

Marvell first bringing advanced node technology to infrastructure silicon with its 5nm platform, followed by the release of several 5-nanometer designs and the profolio of the first silicon infrastructure product lineup based on TSMC’s 3-nanometer process.

“Tomorrow’s artificial intelligence workloads will require significant and substantial gains in performance, power, area, and transistor density. The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure capable of delivering on the promise of AI,” said Sandeep Bharathi, chief development officer at Marvell.

• TSMC

TSMC commenced mass production of its 3-nanometer process in 2022, with profitability realized starting from the third quarter of 2023. By the fourth quarter of 2023, the 3-nanometer process contributed to 15% of wafer revenue, and its revenue share has been steadily increasing.

According to TrendForce, the foundry market is expected to grow by 7% in 2024, largely attributed to TSMC’s ramp-up of its 3-nanometer process. This has further increased TSMC’s market share.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures. It is anticipated that N2 will commence mass production in 2025, leading the industry in terms of density and energy efficiency.

The N2 backside power delivery solution is slated for release in the latter half of 2025 and is expected to enter mass production in 2026, primarily targeting the High-Performance Computing (HPC) sector.

Furthermore, due to the current high demand for 2-nanometer processes from all AI innovators worldwide surpassing that for 3-nanometer processes, almost all AI innovators are collaborating with TSMC on 2-nanometer process technology. The main applications are primarily focused on high-performance computing (HPC) and smartphones.

Consequently, TSMC has announced plans to expand its production capacity for 2-nanometer processes. Originally, two 2-nanometer fabs were planned for the Kaohsiung facility, but now consideration is being given to constructing a third 2-nanometer fab.

• Samsung

Samsung commenced mass production of its 3-nanometer process in June 2022. According to the latest industry reports, Samsung has developed a “second-generation 3-nanometer” process, renamed as “2-nanometer”, with plans for mass production before the end of this year.

At the 2023 Samsung Foundry Forum, Samsung Electronics unveiled the latest roadmap for its 2-nanometer process. Samsung Electronics President and Head of Foundry Business, Siyoung Choi, disclosed that Samsung will first mass-produce 2-nanometer chips for mobile terminals starting from 2025. Subsequently, in 2026, the technology will be applied to high-performance computing (HPC) products, followed by expansion to automotive chips by 2027.

Unlike TSMC, which opted for Gate-All-Around (GAA) structure at the outset of its 2-nanometer process, Samsung has been utilizing GAA structure since its 3-nanometer process. This suggests that Samsung may have more experience in new structures compared to TSMC, thus giving Samsung an advantage in its 2-nanometer node.

In the past, when Samsung Electronics transitioned from 7-nanometer to 5-nanometer process technology in 2020, the second generation 7-nanometer process technology was renamed as 5-nanometer process technology.

Samsung Electronics’ 7-nanometer process technology became the world’s first to use Extreme Ultraviolet (EUV) lithography in 2019, making it more stable and enabling the company to further shrink transistor sizes. This was also the reason for renaming the second generation 7-nanometer process to 5-nanometer process at that time.

A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.

It is reported that PFN has been collaborating with TSMC since 2016, but this year, it has decided to produce the next generation of AI chips at Samsung’s 2-nanometer node. According to the agreement, Samsung will utilize its latest 2-nanometer chip fab technology to manufacture AI accelerators and other AI chips for PFN.

• Intel

As per Intel’s previously announced plans, the company aims to catch up with and surpass TSMC by 2024 or 2025. At this year’s “Direct Connect” conference hosted by Intel Foundry Services, the company unveiled its latest technological roadmap.

Intel has reported that its primary product, Clearwater Forest, which is under the 18A process, has been completed and is set for production in 2025. Intel’s 18A process is often compared with TSMC’s N2 (2-nanometer) and N3P (3-nanometer) processes in terms of performance, with each company advocating for its own advantages.

Intel CEO Pat Gelsinger emphasizes that both 18A and N2 utilize GAA transistors (RibbonFET), but the 1.8-nanometer node will adopt BSPND, a backside power delivery technology that optimizes power and clock. TSMC, on the other hand, believes that its N3P (3-nanometer) technology will rival Intel’s 18A in power consumption, performance, and area (PPA), while its N2 (2-nanometer) will surpass it in all aspects.

Additionally, Intel’s 20A manufacturing technology is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and backside power delivery network (BSPDN). These aim to achieve higher performance, lower power consumption, and increased transistor density.

Meanwhile, Intel’s 18A production node aims to further refine the innovations of 20A and provide additional PPA improvements from late 2024 to early 2025. Per Intel’s statements regarding its fab processes, its 2-nanometer technology is expected to be the earliest to debut.

Of particular note, Intel announced for the first time at the conference the development of 14A (1.4nm) and its evolutionary version, 14A-E. Intel’s 14A process is the industry’s first node to utilize ASML High-NA EUV lithography tools, making Intel the first company in the industry to acquire cutting-edge High-NA tools. Intel expects to develop 14A by 2027.

• Rapidus

In addition to the aforementioned semiconductor foundries, a Japanese company, Rapidus, is worth noting as well. Established in August 2022, Rapidus was jointly founded by eight Japanese companies including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND Flash giant Kioxia, and Mitsubishi UFJ.

On January 22nd of 2024, Rapidus President Junichi Koike announced during a press conference that construction of the Rapidus 2-nanometer chip fab in Japan is progressing smoothly, and the trial production line is scheduled to commence operations in April 2025 as planned. Additionally, there are plans for the construction of a second and third facility in the future.

In September of last year, Rapidus began construction of Japan’s first logic chip fab, “IIM-1,” in Chitose City, Hokkaido, capable of producing chips below 2 nanometers. It is reported that the fab is expected to be completed by December of this year.

Previously, Rapidus signed a collaboration agreement with IBM to develop technology based on IBM’s 2-nanometer process. IBM had already introduced the world’s first 2-nanometer process chip back in 2021. Similarly, IBM’s 2-nanometer process also utilizes GAA (Gate-All-Around) structure. This partnership provides Rapidus with the technical support necessary for advanced process development.

Read more

• [News]The 2nm Semiconductor Foundry Race Between TSMC, Samsung, Rapidus Begins with an Equipment Battle

(Photo credit: TSMC)

Fueled by an AI-driven inventory stocking frenzy across the supply chain, TrendForce reveals that Q2 revenue for the top 10 global IC design powerhouses soared to US $38.1 billion, marking a 12.5% quarterly increase. In this rising tide, NVIDIA seized the crown, officially dethroning Qualcomm as the world’s premier IC design house, while the remainder of the leaderboard remained stable.

AI charges ahead, buoying IC design performance amid a seasonal stocking slump

NVIDIA is reaping the rewards of a global transformation. Bolstered by the global demand from CSPs, internet behemoths, and enterprises diving into generative AI and large language models, NVIDIA’s data center revenue skyrocketed by a whopping 105%. A deluge of shipments, including the likes of their advanced Hopper and Ampere architecture HGX systems and the high-performing InfinBand, played a pivotal role. Beyond that, both gaming and professional visualization sectors thrived under the allure of fresh product launches. Clocking a Q2 revenue of US$11.33 billion (a 68.3% surge), NVIDIA has vaulted over both Qualcomm and Broadcom to seize the IC design throne.

Qualcomm’s Q2 took a hit as the Android smartphone sector grappled with dwindling demand and Apple’s modem pre-purchases resulted in a subdued seasonal rhythm. Consequently, their revenue slid by 9.7%, rounding off at about US$7.17 billion. Broadcom, while benefiting from AI-ignited demand for high-end switches and routers, faced headwinds with revenue drops in server storage, broadband, and wireless. The result was a second-quarter revenue that essentially mirrored the previous quarter at around US$6.9 billion.

AMD’s Q2 performance plateaued at about $5.36 billion, weighed down by a slump in gaming GPU sales and its embedded segment operations. Conversely, MediaTek, after several quarters of inventory recalibration, witnessed a resurgence with components like TV SoCs and Wi-Fi stabilizing. The added impetus of urgent TV orders and escalating shipments for mobile phones, smart platforms, and power management ICs boosted MediaTek’s Q2 to a solid US$3.2 billion.

Marvell, though buoyed by AI deployments in data centers, faced headwinds with a decline in On-Premise Servers (enterprise private clouds). End-user demand remained frail, and with sectors like data centers, telecom infrastructure, and enterprise networking facing revenue drops, Marvell’s Q2 took a 1.4% hit, culminating at roughly $1.33 billion.

Taiwan’s IC design stalwart Novatek flourished as customers replenished TV-related inventories and ushered in novel products such as OLED DDI. Realtek, drawing strength from supply chain restocking of PC/NB-centric ICs, reported quarterly growths of 24.7% and 32.6%, respectively. Yet, without substantial signs of a holistic revival in end-sales and inventory restocking, growth in H2 seems set to face challenges.

Will Semiconductor secured the ninth spot with a Q2 revenue of $528 million, registering a modest decline of about 1.9%. Hot on its heels is the US-based power IC maestro, MPS, with its Q2 revenue tallying up to $441 million—a slip of approximately 2.2%.

Peering into Q3, while inventory levels across companies paint a rosier picture than H1, a pervasive end-user demand slump urges caution. However, a silver lining emerges with CSPs, internet titans, and private firms flocking to generative AI and large language models. As these high-value AI offerings gain traction, TrendForce projects that the top ten global IC design giants will continue their double-digit ascent in Q3, potentially reaching record-breaking figures.

For more information on reports and market data from TrendForce’s Department of Semiconductor Research, please click here, or email Ms. Latte Chung from the Sales Department at lattechung@trendforce.com