As the demand for memory chips used in AI remains strong, prompting major memory companies to accelerate their pace on HBM3e and HBM4 qualification, SK hynix CEO Kwak Noh-jung stated on August 7 that driven by the high demand for memory chips like high-bandwidth memory (HBM), the market is expected to stay robust until the first half of 2025, according to a report by the Korea Economic Daily.

However, Kwak noted that the momentum beyond 2H25 “remains to be seen,” indicating that the company needs to study market conditions and the situation of supply and demand before making comments further. SK hynix clarified that was not an indication of a possible downturn.

According to the analysis by TrendForce, HBM’s share of total DRAM bit capacity is estimated to rise from 2% in 2023 to 5% in 2024 and surpass 10% by 2025. In terms of market value, HBM is projected to account for more than 20% of the total DRAM market value starting in 2024, potentially exceeding 30% by 2025.

SK hynix, as the current HBM market leader, said earlier in its earnings call in July that its HBM3e shipment is expected to surpass that of HBM3 in the third quarter, with HBM3e accounting for more than half of the total HBM shipments in 2024. In addition, it expects to begin supplying 12-layer HBM3e products to customers in the fourth quarter.

The report notes that for now, the company’s major focus would be on the sixth-generation HBM chips, HBM4, which is under development in collaboration with foundry giant TSMC. Its 12-layer HBM4 is expected to be launched in the second half of next year, according to the report.

Samsung, on the other hand, had been working since last year to become a supplier of NVIDIA’s HBM3 and HBM3e. In late July, it is said that Samsung’s HBM3 has passed NVIDIA’s qualification, and would be used in the AI giant’s H20, which has been developed for the Chinese market in compliance with U.S. export controls. On August 6, the company denied rumors that its 8-layer HBM3e chips had cleared NVIDIA’s tests.

Notably, per a previous report from the South Korean newspaper Korea Joongang Daily, following Micron’s initiation of mass production of HBM3e in February 2024, it has recently secured an order from NVIDIA for the H200 AI GPU.

Read more

• [News] SK hynix, TSMC, and NVIDIA Reportedly Forge Alliance to Develop Next-Generation HBM
• [News] SK hynix Secures up to USD 450 Million Funding for Indiana Packaging Facility under CHIPS Act

(Photo credit: SK hynix)

Per a report from Reuters, Intel is said to be receiving the second new High-NA EUV equipment from ASML, costing EUR 350 million (~USD 383 million).

According to Intel’s earnings call on August 1, CEO Pat Gelsinger stated that Intel began receiving the first large equipment in December, and the installation process would take several months, which is expected to bring about a new generation of more powerful computer chip.

Gelsinger noted during the call that the second High-NA equipment is about to enter the facility in Oregon. Due to the poor stock performance following Intel’s earnings report, this statement did not attract much attention.

Previously, a senior executive from ASML once mentioned in July that the company already begun shipping the second High NA equipment to an unnamed customer, but would only record revenue for the first set this year. However, there are still some uncertainties regarding when the customer will adopt this equipment.

ASML has already received orders for over ten High-NA equipment from customers including TSMC, Samsung, Intel, Micron, and SK Hynix. Intel plans to use this technology for mass production by 2027, and TSMC is also set to receive the equipment this year, the time to put into production has not been disclosed, though.

ASML executive Christophe Fouquet stated on July 17 that DRAM memory chip manufacturers, which could refer to Samsung, SK Hynix, or Micron, are expected to start using High-NA equipment by 2025 or 2026.

Read more

• [News] ASML Slightly Beats Q2 Earnings Forecasts, with Full-Year Outlook Unchanged
• [News] Price for ASML’s Hyper-NA EUV Rumored to Double, Causing TSMC, Samsung and Intel to Hesitate

(Photo credit: ASML)

According to a report from Economic Daily News, Innolux President James Yang announced on August 5 that the company is advancing its semiconductor fan-out panel-level packaging (FOPLP) with three key processes, targeting to enter mass production as soon as year-end.

The chip-first process technology, set to be the first to reach mass production by the end of this year, is expected to significantly contribute to revenue by the first quarter of next year.

Additionally, the RDL-first process, which target mid-to-high-end products, is anticipated to enter mass production within one to two years. The most technically challenging Through-Glass Via (TGV) process, being developed in collaboration with partners, will require another two to three years before it can be mass-produced.

At yesterday’s earnings call, there was significant interest in whether Innolux’s 4th Plant in Tainan (5.5-generation LCD panel plant) would be sold to Micron or TSMC.

Innolux Chairman Jim Hung stated that, in addition to quantifying the value of the sale, it is also important to consider the qualitative aspect, such as the potential new business opportunities that the deal could bring for both parties.

He further pointed out that while 5.5-generation plants are not the most competitive in the panel industry, they could still be valuable to other manufacturers. The sale of this asset is expected to contribute to Innolux’s non-operating income.

Regarding the recent focus on FOPLP (Fan-Out Panel-Level Packaging) mass production progress, Jim Hung emphasized that Innolux’s technology is already prepared.

James Yang explained that Innolux’s panel-level fan-out packaging technology will initially be applied to mid-to-low-end products, with plans to later expand into mid-to-high-end products.

He added that by entering the FOPLP field, Innolux aims for this technology to become a part of the AI PC industry, viewing the asset disposal as an opportunity to develop new business models and collaborations.

Previously reported by Economic Daily News, Innolux has been promoting the transformation of its fully depreciated old plants. The 3.5-generation line at the Tainan facility has been repurposed for advanced packaging with FOPLP, and the 4-generation line has been converted to produce X-ray sensors (through Raystar Optronics), both of which are related to semiconductor products.

Read more

• [News] Innolux Confirms Sale of Tainan Plant 4, with Micron & TSMC Reportedly in the Bidding Stage
• [News] Venturing into AI, Innolux Reportedly Partners with Memory Giants, While Its 4th Plant in Tainan to Focus on Packaging Applications

(Photo credit: Innolux)

A previous report from Economic Daily News once reported that, Innolux is set to sell its 4th Plant in Tainan (5.5-generation LCD panel plant), which was closed in 2023. Moreover, the report has cited rumors in the market, claiming that both Micron and TSMC have been actively exploring the acquisition.

Eariler on August 1st, the latest report from MoneyDJ further suggests that TSMC is almost certain to secure the deal, primarily to expand its CoWoS capacity. Regarding this matter, neither company has commented on these market rumors.

On July 30, Innolux announced its plan to dispose of the TAC plant-related real estate at the Southern Taiwan Science Park (STSP) D section, so as to bolster operational funds. To expedite the process and meet business needs, the board authorized Chairman Jim Hung to negotiate terms and sign relevant contracts with potential buyers.

Reportedly, the sale price must not be lower than the asset’s book value in the most recent financial statements, taking into account professional valuation reports and market information.

The recent trend of FOPLP (Fan-Out Panel Level Packaging) is said to have fueled speculation and discussions about Innolux’s plant sale, leading to rumors that TSMC is on the verge of announcing the purchase.

Yet, per MoneyDJ, TSMC’s current FOPLP applications in the AI field primarily involve stacking on rectangular substrates, integrating them into 2.5D and 3D packages. Initially, TSMC prefers to complete the entire FOPLP process in-house, integrating the front-end and back-end technologies of the 3D fabric platform.

For Innolux, besides gaining considerable non-operating income, this opportunity also raises the prospect of future collaboration.

Notably, this rumored move comes as construction at TSMC’s first P1 plant in the Southern Taiwan Science Park’s Chiayi Campus was halted due to the discovery of potential archaeological remains.

With P1 construction paused, TSMC has prioritized the construction of the second plant (P2). However, current capacity is very tight, and the time required to complete and ramp up P2 to mass production may not meet customer demand. The long-term substantial demand has driven TSMC to seek additional suitable locations in advance.

It is indicated by MoneyDJ that though TSMC’s Chiayi plant is currently facing delays due to the archaeological site issue, Chiayi is still planned to be a major hub for CoWoS production in the long term, with six phases planned. Previously, the company had considered expanding SoIC (System on Integrated Chips) production in Yunlin, but has recently decided to put those plans on hold.

Overall, the latest industry estimates suggest that CoWoS monthly capacity could reach about 35,000 to 40,000 wafers this year. On 2025, if outsourcing to packaging and testing subcontractors is included, capacity could potentially exceed 60,000 wafers, or even more next year.

Read more

• [News] Innolux Confirms Sale of Tainan Plant 4, with Micron & TSMC Reportedly in the Bidding Stage
• [News] TSMC Halts Chia-Yi Plant Construction Due to Relic Found, Quickly Initiates Preparation for 2nd Plant

(Photo credit: Innolux)

As the battle of HBM intensifies between memory giants, the competition of NAND is also heating up. According to a report by Korean media outlet etnews, SK hynix is developing 400-layer NAND flash memory, aiming to get the technology ready for mass production by the end of 2025.

Citing sources familiar with the matter, the report notes that SK hynix is currently working with supply chain partners to develop process technologies and equipment needed for 400-layer and above NANDs. As the company plans to apply hybrid bonding to achieve the breakthrough, many packaging materials and components suppliers are expected to enter the new supply chain.

According to the report, SK hynix is reviewing new materials for bonding and various technologies for connecting different wafers, including polishing, etching, deposition, and wiring. With the goal of getting the technology and infrastructure ready by the end of next year, full-scale production for the 400-layer NAND is anticipated to begin in the first half of 2026.

Currently, the Big Three in the memory sector are all trying to push the boundaries on the layers of NAND. Earlier in April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), with the number of layers reaching 290. For now, the company aims to stack V-NAND to over 1000 layers by 2030.

Micron, on the other hand, has announced the 2650 client SSD, its first product built from 276-layer 3D NAND on July 30^th. Japanese memory chipmaker Kioxia, after successfully increasing the number of 3D NAND layers to 218 in 2023, even stated that achieving a 1,000-layer level by 2027 would be possible.

In August, 2023, SK hynix showcased its sample of the world’s first 321-layer NAND product. Now, as the limit is expected to be pushed up to 400 layers, the company plans to apply hybrid bonding to the manufacturing, which adopts a “wafer-to-wafer” (W2W) structure, etnews notes.

According to the report, until now, SK hynix has been stacking cells on top of the peripherals, the driving circuit area, using the method of “Peripheral Under Cell (PUC)” to manufacture NAND. The structure is similar to a mixed-use high-rise apartment where the peripheral (commercial space) is at the bottom and the cells (residential units) are stacked on top.

However, as the number of NAND layers increases, the peripheral is prone to be damaged during the cell stacking process due to the high heat and pressure generated during the cell process, the report explains.

Therefore, SK hynix plans to apply hybrid bonding to overcome the issues. By implementing cells and peripherals on separate wafers and then bonding the two wafers together, the method allows the peripheral wafer that drive the cells to be separately manufactured, thus enabling a stable increase in NAND layers.

Regarding the progress on the development of 400-layer NAND, SK hynix stated that it cannot confirm details about its technology development or mass production timeline, the report notes.

Read more

• [News] SK Hynix Plans to Manufacture 3D NAND over 400 Layers at -70°C with the Help of TEL
• [News] Outpacing Samsung or the End of Race? Kioxia Aims 1000-layer NAND by 2027

(Photo credit: SK hynix)