According to a report from Reuters on July 4, consensus from 27 analysts compiled by LSEG SmartEstimate indicates that driven by the surge in demand for AI technology and the resulting rebound in memory prices, Samsung Electronics’ operating profit for Q2 2024 (ending June 30) is projected to skyrocket by 1,213% from KRW 670 billion in the same period last year to KRW 8.8 trillion (roughly USD 6.34 billion), marking the highest since Q3 2022.

Other memory giants are also optimistic about the operation afterwards. Take Micron as an example. Regarding the AI frenzy, Micron CEO Sanjay Mehrotra claimed that in the data center sector, rapidly growing AI demand enabled the company to grow its revenue by over 50% on a sequential basis.”

Mehrotra is also confident that Micron can deliver a substantial revenue record in fiscal 2025, with significantly improved profitability underpinned by our ongoing portfolio shift to higher-margin products.

On the other hand, SK Group also stated that by 2026, the group will invest KRW 80 trillion in AI and semiconductors, while continuing to streamline its businesses to increase profitability and return value to shareholders.

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• [News] SK Hynix to Invest USD 75 Billion in AI Push, with 80% of It Flooding into HBM
• [News] Memory Giant Micron’s 3Q24 Earnings Report Released, Outlook Slightly Better Than Expected

(Photo credit: Samsung)

According to a report from the Korean media outlet The Chosun Daily, Chinese company Huawei plans to collaborate with memory manufacturer Wuhan Xinxin Semiconductor Manufacturing Co. (XMC) to produce High Bandwidth Memory (HBM) semiconductors. Additionally, Jiangsu Changjiang Electronics Technology (JCET) and Tongfu Microelectronics, which are developing CoWoS advanced packaging technology, are also participating in the project.

CoWoS is a high-precision technology that integrates graphics processing units (GPUs) and HBM on a single substrate. This enhances computational performance, saves space, and reduces power consumption. Currently, the CoWoS technology developed by leading foundry TSMC is used in the production of AI chips for GPU giant NVIDIA.

In May 2023, according to another report from Reuters, China’s leading DRAM company CXMT (ChangXin Memory Technologies) collaborated with Tongfu Microelectronics to develop HBM chip samples. Additionally, tech media outlet The Information reported earlier that a series of Chinese companies, led by Huawei, plan to mass-produce HBM and increase China’s HBM output by 2026.

Furthermore, in March 2023, XMC announced the construction of an advanced HBM manufacturing plant, which is expected to produce 3,000 12-inch wafers per month.

The report further emphasizes that China is still in the early stages of HBM development. However, under the technological restrictions imposed by the United States in the semiconductor and artificial intelligence sectors, Huawei and a series of Chinese semiconductor companies’ move into HBM production has attracted close attention.

Currently, South Korean companies SK Hynix and Samsung Electronics control most of the global HBM market share, indicating that Huawei’s plan to develop HBM still has a long way to go.

Per TrendForce’s data, the three major HBM manufacturers held market shares are as follows: In 2023, SK Hynix and Samsung each held around 47.5%, while Micron’s share was roughly 5%. Still, forecasts indicate that SK Hynix’s market share in 2024 will increase to 52.5%, while Samsung’s will decrease to 42.4%.

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• [News] Micron’s HBM Expansion at Full Throttle: Rumored to Expand in US, Malaysia Also an Option
• [News] XMC Initiates IPO Plan, Potentially Becoming China’s First HBM Foundry

(Photo credit: XMC)

After Micron’s announcement of constructing two new fabs in the U.S. in 2022, the memory giant has now provided more details regarding their production timeline. According to the information the company disclosed in its Q3 FY24 financial report and its conference call, the fabs in Idaho and New York target to start operation between 2026 and 2029, a report from AnandTech noted.

“Fab construction in Idaho is progressing well, and we are diligently working to complete the regulatory and permitting processes in New York,” said Sanjay Mehrotra, CEO of Micron, during the company’s conference call with investors and financial analysts. However, the company admits that the Idaho fab will not contribute to meaningful supply until FY27, while and the New York fab is not expected to contribute to bit supply growth until FY28 or later.

AnandTech further noted that as Micron’s fiscal year 2027 begins in September 2026, the new fab near Boise, Idaho, will likely commence operations between September 2026 and September 2027, while the New York fab is expected to begin operations afterwards. Namely, Micron’s U.S. memory fabs are projected to start operations between late 2026 and 2029.

According to an earlier report by Bloomberg, Micron is expected to receive over USD 6 billion in funding through the “Chips Act” from the Department of Commerce to assist with the costs of local factory projects, as part of efforts to bring semiconductor production back to U.S. soil.

Though its U.S. fabs may not start operation soon, Micron does confirm the strong momentum from HBM, saying that its HBM production capacity has been fully booked through 2025, according to another report by TheElec. The company would be the second memory giant to make such a statement, after SK hynix.

Micron claims that it expect to generate “several hundred million dollars” of revenue from HBM in FY24, and “multiple $Bs” in revenue from HBM in FY25. The company has already sampled its 12-high HBM3E product and expect to ramp it into high volume production in 2025, as it is also confident to maintain the technology leadership with HBM4 and HBM4E.

To support the strong market demand as well as preparing for the mass production for its U.S. fabs, Micron expects to increase its capital spending materially next year, with capex around mid-30s % range of revenue for FY25, which will support HBM assembly and test equipment, fab and back-end facility construction as well as technology transition investment to support demand growth, the company said.

Micron states that its average quarterly capex in FY25 to be meaningfully above the Q4 2024 level of USD 3 billion, which means its capex would be around USD 12 billion, reporting a strong 50% YoY growth comparing to the USD 8 billion in FY24.

Read more

• [News] Memory Giant Micron’s 3Q24 Earnings Report Released, Outlook Slightly Better Than Expected
• [News] Micron Reportedly to Receive Over USD 6 Billion in US Chip Funding

(Photo credit: Micron)

On June 26, American memory manufacturer Micron announced its financial results for the third quarter of the 2024 fiscal year (ending May 30, 2024) after the market closed: revenue increased by 82% year-over-year (17% quarter-over-quarter) to $6.811 billion; Non-GAAP diluted earnings per share (EPS) were reported at $0.62, better than the $0.42 of the second quarter of the 2024 fiscal year and the diluted loss per share of $1.43 in the third quarter of the 2023 fiscal year.

Micron further estimates that for the fourth quarter of the 2024 fiscal year, revenue and Non-GAAP diluted EPS will be $7.6 billion (plus or minus $200 million) and $1.08 (plus or minus $0.08), respectively.

Per a Bloomberg report on June 26th, some sources expect Micron’s fourth-quarter revenue to exceed USD 8 billion.

Micron CEO Sanjay Mehrotra stated in a press release that the improving market conditions and strong price and cost execution drove the financial outperformance. Reportedly, Micron’s total fiscal Q3 revenue was USD 6.8 billion, up 17% sequentially and up 82% year over year.

Mehrotra also noted that Micron’s market share for high-margin AI-related product categories such as HBM (high-bandwidth memory), high-capacity DIMMs and data center SSDs continue to rise. Meanwhile, Micron is also gaining share in data center SSD, reaching new revenue and market share records in this important product category.

Mehrotra stated during the earnings call that strong AI-driven demand for data center products has led to tight capacity for advanced processes. Therefore, despite steady recent demand for personal computers (PCs) and smartphones, Micron expects prices to continue rising throughout 2024 (January to December).

Micron CEO Sanjay Mehrotra further addressed, “In the data center, rapidly growing AI demand enabled us to grow our revenue by over 50% on a sequential basis.” He then pointed out, “…we can deliver a substantial revenue record in fiscal 2025, with significantly improved profitability underpinned by our ongoing portfolio shift to higher-margin products.”

Looking ahead to 2025, the growing demand for AI PCs, AI smartphones, and data center AI creates a favorable environment, giving Micron confidence in achieving substantial revenue records in the 2025 fiscal year. This is expected to significantly boost profitability as the product mix continues to shift towards higher-margin products.

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• [News] ASMPT Reportedly Provided Demo TC Bonder to Micron for HBM Production
• [News] Micron’s HBM Expansion at Full Throttle: Rumored to Expand in US, Malaysia Also an Option

(Photo credit: Micron)

After ending production cuts amidst a recovery in the memory industry, Kioxia disclosed its plans on the 3D NAND roadmap last week. According to reports from PC Watch and Blocks & Files, Kioxia stated that achieving a 1,000-layer level by 2027 would be possible.

According to the reports, the number of 3D NAND layers has generally increased from 24 in 2014 to 238 in 2022, representing a tenfold rise over eight years. Kioxia stated that achieving a 1,000-layer level by 2027 would be possible at a rate of increase of 1.33 times per year.

The Japanese memory chipmaker seems to be more ambitious than Samsung regarding the battle of layers. In May, Samsung revealed its target to release advanced NAND chips with over 1000 layers by 2030. According to Wccftech, the South Korean memory giant plans to apply new ferroelectric materials on the manufacturing of NAND to achieve this goal.

According to the latest analysis from TrendForce, Kioxia has benefited from the recovery of the memory industry, recently receiving subsidies from the Japanese government and additional financing from a consortium of banks. Furthermore, the company plans to launch an IPO by the end of the year. These measures have provided Kioxia with ample financial resources to pursue technological advancements and cost optimization.

TrendForce further notes that Kioxia has ambitious plans to achieve 1000-layer technology by 2027, which is the highest number of layers announced by any manufacturer so far. However, to reach the milestone, it will be necessary to transition from TLC (3 bits per cell) to QLC (4 bits per cell), and possibly even to PLC (5 bits per cell). The technical challenges involved are significant, and whether Kioxia can achieve this market milestone by 2027 remains to be seen.

The Battle of Layers between Memory Giants

Kioxia and its partner Western Digital showcased their 218-layer technology in 2023 following the 162-layer milestone. Its current announcement to achieve the 1000-layer technology by 2027 would be a huge leap from that.

The battle of layers between memory giants has been intensifying as other memory heavyweights had already surpassed the 200-layer milestone. Earlier in April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), with the number of layers reaching 290, according an earlier report by The Korea Economic Daily. For now, the company aims to stack V-NAND to over 1000 layers by 2030.

SK Hynix unveiled the world’s highest-layer 321-layer NAND flash memory samples in August 2023, claiming to have become the industry’s first company developing NAND flash memory with over 300 layers, with plans for mass production by 2025. Micron has also started to mass produce its 232-layer QLC NANDs in 2024.

Uncertainties behind Kioxia’s Optimism

However, to Kioxia, there are more challenges to overcome, as technological obstacles and Western Digital’s stance add uncertainties to its ambition. According to the report from Blocks & Files, increasing density in a 3D NAND die involves more than just adding layers, as each layer’s edge must be exposed for memory cell electrical connectivity. This results in a staircase-like profile, and as the number of layers grows, the die area needed for the staircase expands as well.

Therefore, to increase density, it is necessary to shrink the cell size both vertically and laterally, and to raise the bit level as well. All these scaling factors, including layer counts, vertical cell size reduction, lateral cell size reduction, and cell bit level increases, present their own technological challenges.

Moreover, according to Blocks & Files, WD has concerns regarding the manufacturing capital costs and the return on investment from selling chips and SSDs made with the fabricated NAND dies.

Citing Western Digital EVP Robert Soderbery in June, the report noted that in the 3D era, NAND manufacturing requires higher capital intensity but offers a lower cost reduction as bit density increases. The company even described the situation as the “end of the layers race,” indicating that there would be a slowdown in the rate of NAND layer count increases to optimize capital deployment.

How long would the battle of layers continue, and how far would it go? Technological breakthroughs as well as the willingness to endure higher capital intensity while the cost reduction being relatively limited may be key.

Read more

• [News] NAND Flash Market Competition Intensifies, as SK Hynix, Samsung Strive to Meet AI Demand
• [News] With Memory Market Recovering, Kioxia Has Reportedly Ceased Production Cuts and Secured Bank Lending

(Photo credit: Kioxia)