TSMC is set to offer a new round of its CyberShuttle prototyping service in September. According to sources cited in a report from Commercial Times, it’s revealed that, as per usual practice, there are two opportunities each year, in March and September, for customers to submit their projects. It is indicated that the highlight this time is expected to be the 2nm process, providing leading companies with an opportunity to gain an edge.

TSMC’s 2nm technology is progressing smoothly, with the new Hsinchu Baoshan plant on track for mass production next year. Previously, there were rumors indicating that Apple is considering adopting 2nm chips in 2025, with the iPhone 17 series potentially being among the first devices to use them.

Reportedly, both TSMC’s N2P and A16 technologies are expected to enter mass production in the second half of 2026, offering improvements in power efficiency and chip density.

ASIC companies are eagerly participating in CyberShuttle this time, even though customer intentions for the first 2nm tape-out are still unconfirmed. However, this technology will likely maintain TSMC’s leadership in advanced processes, securing its future technological advantage.

CyberShuttle, also known as MPW (Multi-Project Wafer), refers to the process of placing chips from different customers onto the same test wafer. This approach not only allows for the shared cost of photomasks but also enables rapid chip prototyping and verification, enhancing customers’ cost efficiency and operational effectiveness.

Based on TSMC’s official information, the CyberShuttle prototyping service significantly reduces NRE costs by covering the widest technology range (from 0.5um to 7nm) and the most frequent launch schedule (up to 10 shuttles per month), all through the Foundry segment’s most convenient on-line registration system.)

TSMC’s CyberShuttle prototyping service also validate the sub-circuit functionality and process compatibility of IP, standard cell libraries and I/Os, reducing prototype costs by up to 90%. TSMC states that their current CyberShuttle service covers the broadest range of technologies and can offer up to 10 shuttles per month.

TSMC’s 2nm technology is expected to make its debut in September, offering opportunities for test chips.

Per the report from Commercial Times, IC design companies have pointed out that, unlike the familiar FinFET (Fin Field-Effect Transistor) structure, the industry is transitioning to the Gate-All-Around FET (GAAFET) structure, making it crucial for the market to quickly adapt.

This also allows IC design companies to provide related products to end customers, demonstrating their 2nm design capabilities.

ASIC companies have also revealed that, based on CyberShuttle data, the number of advanced process projects below 7nm is relatively small, with mature processes still dominating.

This suggests that future competition will likely focus on a few leading companies. Those who miss the first wave of 2nm technology may fall behind their competitors by up to six months, making securing a spot on the Shuttle even more critical.

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(Photo credit: TSMC)

Despite the uncertainties in the semiconductor market, there is still an intense global competition in the development of advanced semiconductor manufacturing processes. TSMC as one of the key players in the foundry industry is actively advancing its next-generation 2nm process. According to market rumors, the schedule for the first tool-in at Hsinchu Baoshan Fab and Kaohsiung Fab has been established, along with a finalized production capacity plan.

CNA has reported that TSMC’s 2nm process will be deployed in the Phase 2 Expansion Area of the Baoshan Site at the Hsinchu Science Park. The first tool-in is scheduled for April 2024. Industry sources have revealed that the initial production capacity for this process will be around 30,000 wafers per month, with mass production planned for the following year.

In addition, TSMC’s fab in Kaohsiung has notified equipment suppliers that this facility is set to begin in the third quarter of 2025. According to MoneyDJ, the pilot run is planned for the end of the same year, with the aim of achieving mass production in 2026. The Kaohsiung fab will adopt the N2P process, which is an enhanced version of the 2nm process with the backside power rail technology. The initial monthly production capacity is also expected to be around 30,000 wafers.

According to previous disclosures made by TSMC during financial calls, the company has developed a backside power rail solution for the N2 process, which is particularly suitable for high-performance computing (HPC) applications. This innovative technology is expected to boost speed by 10% to 12% and increase logic density by 10% to 15%. TSMC plans to introduce the backside power rail solution to customers in the latter half of 2025, with mass production scheduled for 2026. This timetable aligns with recent rumor circulating in the supply chain.

In addition to the latest progress on the N2P process, TSMC made an official announcement at the IEEE International Electron Devices Meeting (IEDM) on December 12th. Specifically, the company revealed its plans to introduce a 1.4nm process as the successor to the 2nm process. As reported by Tom’s Hardware, this new process, named A14, continues the naming convention from the 2nm process (A20). Production using the A14 process is anticipated to take place between 2027 and 2028.

(Image: TSMC)

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