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If you happen to be a technology enthusiast, June would certainly be a month to watch. NVIDIA CEO Jensen Huang, joined by AMD CEO Lisa Su, visited Taiwan to announce their product roadmaps in COMPUTEX 2024. NVIDIA unveiled its new generation Rubin architecture, indicating that the R series products are expected to go into mass production in the fourth quarter of 2025.
On the other hand, AMD introduced its Ryzen AI 300 Series processors with the world’s most powerful Neural Processing Unit (NPU) for next-gen AI PCs, featuring a new Zen 5 CPU, as well as its latest AI chips, MI325X and MI350.
Interestingly enough, on 4 June, the world’s largest semiconductor foundry, TSMC, held its shareholders’ meeting in Hsinchu, Taiwan. When asked about the company’s relationships with NVIDIA and AMD, President C.C. Wei has reaffirmed TSMC’s strong relationships with the two tech giants, saying that the company will prosper with its clients.
What will be the highlights for TSMC’s progress in advanced logic process, and what are some of the most advanced products introduced in COMPUTEX made with TSMC’s advanced nodes? Please proceed to find out more. For now, TSMC’s 3nm seems to be the most popular node.
N3 Family
TSMC’s N3E (the more cost-effective second generation of the 3nm process) entered mass production in the fourth quarter of 2023. On the other hand, N3P (a more advanced version) is scheduled to enter mass production in the second half of 2024. Its yield performance is close to that of N3E, while customer product designs have already been tape-out.
TSMC states that due to N3P’s superior performance, better power consumption and area (PPA) characteristics, most 3nm products will eventually adopt the node. In the future, the industry may expect to see more high-end products manufactured with 3nm.
Regarding capacity, driven by the strong demand from HPC and mobile phone, TSMC has tripled its 3nm capacity in 2024 compared to that of 2023. However, as it is still not enough, the world’s largest semiconductor foundry has been striving to meet customer demand.
Intel’s Lunar Lake/ Arrow Lake
At COMPUTEX 2024, Intel CEO Pat Gelsinger introduced Lunar Lake, its latest AI PC chip, and thank its friend “TSMC” for their full support.
Starting Q3 2024 in time for the holiday season, Lunar Lake will power more than 80 new laptop designs across more than 20 original equipment manufacturers.
In a previous report by Wccftech, Gelsinger stated that Intel has collaborated with TSMC to power up its next-gen CPUs, adopting N3B, the first-generation 3nm process, for Lunar Lake and Arrow Lake.
NVIDIA’s Rubin
On the other hand, NVIDIA’s Rubin GPU architecture is now official: the Rubin GPU will feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, noted by Jensen Huang, CEO of NVIDIA.
Per a report from Wccftech, NVIDIA’s Rubin GPU is expected to utilize TSMC’s CoWoS-L packaging technology, along with its N3 process. Moreover, NVIDIA will use next-generation HBM4 DRAM to power its Rubin GPU.
Regarding NVIDIA’s previous GPUs, according to Commercial Times’ report, H200 and B100 reportedly are said to adopt TSMC’s 4-nanometer and 3-nanometer processes, respectively.
AMD’s MI 325X/ MI350
On 3 June, AMD CEO Lisa Su stated that the company’s relationship with TSMC is “very strong,” even as rumors have been circulating about a potential partnership with Samsung, TSMC’s main competitor.
AMD unveiled the company’s latest AI chip, MI325X, at the opening of COMPUTEX Taipei. Su emphasized that the MI325X boasts 30% faster computing speed compared to NVIDIA’s H200.
Furthermore, she also announced that AMD will release MI350 in 2025, which will be manufactured with TSMC’s 3nm process, while MI400 is expected to follow, launched in 2026.
When asked if AMD intended to procure chips manufactured using Samsung’s 3-nanometer (3nm) gate-all-around (GAA) process, Su reiterated AMD’s commitment to utilizing “the most advanced technology,” saying that AMD is certainly going to use 3 nm, 2 nm, and beyond. She also confirmed that there are several 3nm products currently being developed in collaboration with TSMC.
In addition to TSMC’s collaboration with clients on 3nm, this article also curates TSMC’s progresses on its 2nm node and other advanced processes. More information below:
N2 Family
The N2 process utilizes nanosheet transistors, thus would be able to offer superior energy efficiency. Currently, TSMC’s 2nm technology is progressing smoothly, with nanosheet conversion performance reaching the target of 90%, indicating that the yield exceeds 80%. Mass production is expected in 2025.
In the future, TSMC states that more members of the N2 family will emerge, including applications like N2P and N2X.
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(Photo credit: TSMC)
News
Fueled by the advancement in TSMC’s N3 process technology, the average selling price (ASP) of TSMC’s 12-inch wafers increased to USD 6,611 in the fourth quarter of 2023, registering a year-on-year growth of 22% despite the subdued semiconductor market.
According to a report by TechNews, Bernstein Research has indicated that the current growth in most semiconductor industries stems from the increase in pricing rather than a rise in chip shipment volumes.
As per a report by Tom’s Hardware, the wafer shipment volume of TSMC serves as evidence in many aspects. In the fourth quarter of 2023, TSMC’s shipment of 12-inch wafers was 2.957 million units, lower than the 3.702 million units in the fourth quarter of 2022. This marks the first time since 2020 that TSMC’s 12-inch wafer shipments have fallen below 3 million units. However, the revenue showed only a marginal decline.
Despite a significant 20.1% decrease in the fourth-quarter shipment volume of TSMC’s 12-inch wafers compared to the previous year, the revenue for the quarter reached USD 19.62 billion, only a 1.5% decrease from USD 19.93 billion in the fourth quarter of 2022.
Meanwhile, the average price of TSMC’s processed 12-inch wafers in the fourth quarter of 2023 reached USD 6,611 per unit, surpassing the USD 5,384 per unit in the fourth quarter of 2022. This is attributed to the increased shipment volume of wafers at the N3 process to customers, including Apple.
The report further cites sources indicating that TSMC may charge up to USD 20,000 per wafer manufactured using its N3 process. Although this figure may not be entirely accurate as TSMC’s pricing depends on various factors, the key point is that TSMC’s fees for the N3 process are higher compared to the N4/N5 or N6/N7 process.
Therefore, it can be argued that TSMC’s increase in manufacturing prices for process nodes has played a significant role in driving almost all growth in the semiconductor industry in recent years.
In essence, as time progresses, new process nodes will become increasingly expensive. The total chip shipments from 2019 to 2023 have actually decreased, but the ASP has significantly increased.
In particular, TSMC’s wafer revenue for the fourth quarter of 2023 was notably influenced by its N3 process, contributing 15%, while the N5 and N7 process contributed 39% and 17%, respectively.
This breakdown signifies that the N3 process node generated USD 2.943 billion in revenue for TSMC, the N5 process contributed USD 6.867 billion, and the N7 process brought in USD 3.3354 billion.
Overall, TSMC’s advanced process (N7, N5, N3) accounted for 67% of its total wafer revenue. Among these, revenues from System-on-Chip (SoC) used in smartphones and high-performance computing applications each constituted 43%, automotive chip revenue made up 5%, and IoT chip revenue contributed 5%.
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(Photo credit: TSMC)
News
TSMC, the world’s leading foundry in the 3nm technology, is reportedly experiencing a surge in the number of New Tape-Outs (NTOs) for the 3nm family in 2024, with Clients such as MediaTek, AMD, NVIDIA, Qualcomm, and Intel.
Among the 3nm family, the N3P process, set for mass production in the second half of 2024, is also making significant progress. Rumors suggest that Tesla has been added to the list of customers, with plans to utilize the N3P for the production of next-generation Full Self-Driving (FSD) chips after its launch.
Currently, Tesla has placed orders with TSMC for numerous chips related to electric vehicles. For instance, the supercomputer chip “D1” is utilizing TSMC’s 7nm technology along with advanced packaging processes.
Reportedly, according to industry sources, Tesla’s older FSD chips were initially produced using Samsung’s 14nm process, later upgraded to Samsung’s 7nm process. Subsequently, considering design upgrades, production quality, and scale, Tesla has shifted its HW 4.0 autonomous driving chip production to TSMC, utilizing the 5nm technology family.
The latest information per the report indicates that Tesla has recently initiated a NTO process with TSMC, planning to utilize the N3P for the production of the fifth generation of self-driving vehicle chips. Market expectations are high, with the influx of relevant orders suggesting that Tesla has the potential to become one of TSMC’s major clients.
According to TSMC’s previously disclosed process roadmap, the N3P process is an advanced version within the 3nm family, scheduled for production in 2024. Compared to the N3E, the N3P boasts a 5% improvement in performance, a 5% to 10% reduction in power consumption, and a 1.04 times increase in chip density.
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(Photo credit: TSMC)