Amid the wave of AI applications, the demand for high-performance memory continues to mushroom, with DRAM, represented by HBM, gaining significant traction. Meanwhile, to further meet market demand, memory manufacturers are  poised to embrace a new round of DRAM technological “revolution.”

• 4F Square DRAM being Developed Smoothly

According to a report from Korean media outlet Chosun Biz, Samsung Electronics Vice President Changsik Yoo recently announced that Samsung’s next-generation DRAM technology is progressing well. In addition to the successful mass production of 1b DRAM, the development of 4F Square DRAM technology is also proceeding smoothly, with the initial sample of 4F Square DRAM set to be developed by 2025.

Industry sources cited by WeChat account DRAMeXchange indicate that the early DRAM cell structure was 8F Square, while currently commercialized DRAM mainly uses 6F Square. Compared to these two technologies, 4F Square employs a vertical channel transistor (VCT) structure, which can reduce the chip surface area by 30%.

As the cell area decreases, DRAM density and performance increase. Therefore, driven by applications like AI, 4F Square technology is gradually sought after by major storage manufacturers.

Previously, Samsung stated that many companies are working to transition their technology to 4F Square VCT DRAM, although some challenges need to be overcome, including the development of new materials like oxide channel materials and ferroelectrics.

Industry sources believe that the initial sample of Samsung’s 4F Square DRAM in 2025 might be for internal release. Another semiconductor manufacturer, Tokyo Electron, estimates that DRAM using VCT and 4F Square technology will come out between 2027 and 2028.

Furthermore, earlier media reports mentioned that Samsung plans to apply Hybrid Bonding technology to support the production of 4F Square DRAM. Hybrid Bonding is a next-generation packaging technology referring to vertically stack chips to increase cell density and thus improve performance, which will also exert an influence on the development of HBM4 and 3D DRAM.

• HBM4 on the Horizon

In the era of AI, HBM, particularly HBM3e, has thrived in the memory market, prompting fierce competition among the three major DRAM manufacturers. A new race is now underway, primarily focusing on the next-generation HBM4 technology.

In April of this year, SK Hynix announced a partnership with TSMC to jointly develop HBM4. It is reported that the two companies will first work on performance improvements for the base die fitted at the bottom layer within the HBM package. To focus on the development of next-generation HBM4 technology, Samsung has established a new “HBM Development Team.”

In July, Choi Jang-seok, head of the New Business Planning Group in Samsung Electronics’ memory division, revealed that the company is developing a high-capacity HBM4 memory with a single stack of up to 48GB, expected to go into production next year. Recently, Samsung reportedly plans to use a 4nm advanced process to produce HBM4 logic die. Micron, on the other hand, plans to introduce HBM4 between 2025 and 2027 and transition to HBM4E by 2028.

Aside from manufacturing processes, DRAM manufacturers are actively exploring hybrid bonding technology for future HBM products. Compared to existing bonding processes, hybrid bonding eliminates the need for bumps between DRAM memory layers, instead directly connecting the upper and lower layers, copper to copper. This significantly improves signal transmission speed, better matching the high bandwidth requirements of AI computing.

In April of this year, Korean media outlet The Elec reported that Samsung successfully manufactured a 16-layer stacked HBM3 memory based on hybrid bonding technology, with the memory sample functioning normally. This 16-layer stacked hybrid bonding technology will be used to produce HBM4 at scale in the future. SK Hynix plans to adopt hybrid bonding in its HBM production by 2026. Micron is also developing HBM4 and is considering related technologies, including hybrid bonding, which are all under research at present.

• The Development of 3D DRAM Picks up Steam

3D DRAM (Three-dimensional dynamic random-access memory) represents a new DRAM technology with a novel memory cell structure. Unlike traditional DRAM, which places memory cells horizontally, 3D DRAM vertically stacks memory cells, greatly increasing storage capacity per unit area and improving efficiency. This makes it a key development for the next generation of DRAM.

In the memory market, 3D NAND Flash has already achieved commercial application, while 3D DRAM technology is still under research and development. However, as AI, big data, and other applications enjoy burgeoning growth, the demand for high-capacity, high-performance memory will surge, and 3D DRAM is expected to become a mainstream product in the memory market.

HBM technology has paved the way for the 3D evolution of DRAM, enabling DRAM to transition from traditional 2D to 3D. However, current HBM cannot be considered as true 3D DRAM technology. Samsung’s 4F Square VCT DRAM is closer to the concept of 3D DRAM, but it is not the only direction or goal for 3D DRAM. Memory manufacturers have more ideas and creativity in 3D DRAM.

Samsung plans to achieve the commercialization of 3D DRAM by 2030. In 2024, Samsung showcased two 3D DRAM technologies, including VCT and stacked DRAM. Samsung first introduced VCT technology, then upgraded to stacked DRAM by stacking multiple VCTs together to continuously improve DRAM capacity and performance.

Samsung states that stacked DRAM can fully utilize the Z-axis space, accommodating more memory cells in a smaller area, with a single chip capacity exceeding 100Gb. In May of this year, Samsung noted that it, along with other companies, successfully manufactured 16-layer 3D DRAM, but emphasized that it is not ready for mass production. 3D DRAM is expected to be produced using wafer-to-wafer hybrid bonding technology, and BSPDN (Backside Power Delivery Network) technology is also considered.

Regarding Micron, industry sources cited by DRAMeXchange reveal that Micron has filed for a 3D DRAM patent application different from Samsung’s, aiming to alter the shape of transistors and capacitors without placing cells.

BusinessKorea reported in June that SK Hynix achieved a manufacturing yield of 56.1% for its 5-layer stacked 3D DRAM. This means that out of around 1000 3D DRAMs produced on a single test wafer, about 561 viable devices were manufactured. The experimental 3D DRAM demonstrated characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix disclosed specific numbers and features of its 3D DRAM development.

Besides, American company NEO Semiconductor is also engaging in the development of 3D DRAM. Last year, NEO Semiconductor announced the launch of the world’s first 3D DRAM prototype: 3D X-DRAM. This technology resembles 3D NAND Flash, namely increasing memory capacity by stacking layers, offering high yield, low cost, and remarkably high density.

NEO Semiconductor plans to launch the first generation of 3D X-DRAM in 2025, featuring a 230-layer stack and a core capacity of 128Gb, which is several times higher than the 16Gb capacity of 2D DRAM.

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(Photo credit: SK Hynix)

From the current landscape of publicly available DRAM technologies, the industry is expected to perceive 3D DRAM as one of the solutions to the challenges faced by DRAM technology, marking it as a pivotal direction for the future memory market.

Is 3D DRAM similar to 3D NAND? How will the industry address technological bottlenecks such as size limitations? What are the strategies of major players in the field?

• Understanding 3D DRAM Technology

The circuitry of DRAM consists of a transistor and a capacitor, where the transistor is responsible for transmitting electrical currents to write or read information (bits), while the capacitor stores the bits.

DRAM finds wide application in modern digital electronic devices such as computers, graphics cards, portable devices, and gaming consoles, due to its low cost and high capacity memory.

The development of DRAM primarily focuses on increasing integration by reducing circuit line widths. However, as line widths reach the 10nm range, physical limitations such as capacitor current leakage and interference significantly increase.

To address these issues, the industry has introduced new materials and equipment like high dielectric constant (high-K) deposition materials and Extreme Ultraviolet (EUV) devices.

Nevertheless, from the perspective of chip manufacturers, miniaturizing the manufacturing of 10nm or more advanced chips remains a significant challenge in current technology research and development. Additionally, the competition for advanced processes, particularly at 2nm and below, has intensified recently.

In an era marked by continuous technological advancements, the semiconductor industry has turned its attention to the evolution of NAND technology. To overcome scaling limitations, transistors are transitioning from a planar to a 3D architecture, increasing the number of storage units per unit area. This concept of 3D DRAM architecture has entered the public sphere.

In traditional DRAM, transistors are integrated on a flat plane. However, in 3D DRAM, transistors are stacked into multiple layers, thereby dispersing the transistors. It is believed that adopting a 3D DRAM structure can widen the gaps between transistors, reducing leakage currents and interference.

From a theoretical perspective, 3D DRAM technology breaks the conventional paradigm of memory technology. It is a novel storage method that stacks storage cells above logic units, enabling higher capacities within a unit chip area.

In terms of differentiation, traditional DRAM requires complex operational processes for reading and writing data, whereas 3D DRAM can directly access and write data through vertically stacked storage units, significantly enhancing access speeds. The advantages of 3D DRAM not only include high capacity and fast data access but also low power consumption and high reliability, meeting various application needs.

In terms of application areas, the high speed and large capacity of 3D DRAM will help improve the efficiency and performance of high-performance computing. The compact size and large capacity of 3D DRAM make it an ideal memory solution for mobile devices. The large capacity and low power consumption characteristics of 3D DRAM can meet the real-time data processing and transmission requirements of the Internet of Things (IoT) field.

Furthermore, since the advent of the AI era with ChatGPT, AI applications have surged, and AI servers are expected to become a strong driving force for the long-term growth in storage demand.

Micron’s chief business officer previously stated in an interview with Reuter that a typical AI server has up to eight times the amount of DRAM and three times the amount of NAND that a normal server has.

• Continued Industry Focus on 3D DRAM

The DRAM market remains highly concentrated, currently dominated by key players such as Samsung Electronics, SK Hynix, and Micron Technology, collectively holding over 93% of the entire market share.

According to a report from TrendForce, as of the third quarter of 2023, Samsung leads the global market with a share of 38.9%, followed by SK Hynix (34.3%) and Micron Technology (22.8%).

Currently, 3D DRAM is in its early stages of development, with companies like Samsung actively joining the research and development battleground. The competition is intense as various players strive to lead in this rapidly growing market.

• Samsung: 4F2 DRAM

Since 2019, Samsung has been conducting research on 3D DRAM and announced the industry’s first 12-layer 3D-TSV (Through-Silicon Via) technology in October of the same year. In 2021, Samsung established a next-generation process development research team within its DS division, focusing on research in this field.

At the 2022 SAFE Forum, Samsung outlined the overall 3DIC journey of Samsung Foundry and indicated its readiness to address DRAM stacking issues with a logic-stacked chip, SAINT-D. The design aims to integrate eight HBM3 chips onto one massive interposer chip.

In May 2023, as per sources cited by “The Elec,” Samsung Electronics formed a development team within its semiconductor research center to mass-produce 4F2 structured DRAM.

The goal is reportedly to apply 4F2 to DRAM at 10nm processes or more advanced nodes, as DRAM cell scaling has reached its limit. The report suggests that if Samsung’s 4F2 DRAM storage unit structure research is successful, the chip die area can be reduced by around 30% compared to existing 6F2 DRAM storage unit structures without changing the node.

In October of the same year, at the “Memory Technology Day” event, Samsung Electronics announced its plans to introduce a new 3D structure in the next-generation 10-nanometer more advanced nodes DRAM, rather than the existing 2D planar structure. The aim of this project is to increase the production capacity of a chip by over 100G.

At the “VLSI Symposium” held in Japan last year, Samsung Electronics presented a paper containing research results on 3D DRAM and showcased detailed images of 3D DRAM as an actual semiconductor implementation.

According to a report by The Economic Times, Samsung Electronics recently announced the opening of a new R&D laboratory in Silicon Valley, USA, dedicated to the development of next-generation 3D DRAM.

The laboratory is operated under Silicon Valley’s Device Solutions America (DSA) and is responsible for overseeing Samsung’s semiconductor production in the United States, as well as focusing on the development of new generations of DRAM products.

• SK Hynix – Introducing IGZO as the Channel Material for Future DRAM

Per SK Hynix’s research, the IGZO channel is attracting attention to improve the refresh characteristics of DRAM.

Reportedly, IGZO thin film transistors have been used in the display industry for a long time due to their moderate carrier mobility, extremely low leakage current and substrate size scalability. It can be a candidate for a stackable channel material for future DRAM.

• NEO – 3D X-DRAM Offers 8x Density Boost

NEO Semiconductor, a US memory technology company, introduces its groundbreaking technology, 3D X-DRAM, aimed at overcoming the capacity limitations of DRAM.

3D X-DRAM features the first-ever array structure of DRAM units based on Floating Body Cell (FBC) technology, akin to 3D NAND. Similar to 3D NAND Flash, its logic involves stacking layers to increase memory capacity. The FBC technology in 3D NAND Flash enables the formation of a vertical structure with the addition of a layer mask, offering high yield, low cost, and a significant density boost.

According to Neo’s estimates, the 3D X-DRAM technology can achieve a density of 128 Gb across 230 layers, which is eight times the current density of DRAM. NEO proposes a target of an eightfold capacity increase every decade, aiming to achieve a capacity of 1Tb between 2030 and 2035, representing a 64-fold increase compared to the current core capacity of DRAM.

This expansion is intended to meet the growing demand for high-performance and large-capacity semiconductor storage, especially for AI applications like ChatGPT.

“3D X-DRAM will be the absolute future growth driver for the Semiconductor industry,” said Andy Hsu, Founder and CEO of NEO Semiconductor.

• Japanese Research Team: BBCube 3D Outperforms DDR5 by 30x

A research team at the Tokyo Institute of Technology in Japan has introduced a groundbreaking 3D DRAM stacking design technology called BBCube, which enables superior integration between processing units and DRAM.

The most significant aspect of BBCube 3D lies in achieving a three-dimensional connection between processing units and DRAM instead of the traditional two-dimensional linkages. The team employs an innovative stacking structure while using an innovative stacked structure in which the PU dies sit atop multiple layers of DRAM, all interconnected via through-silicon vias (TSVs).

The overall structure of BBCube 3D is compact, devoid of typical solder microbumps, and utilizes TSVs instead of longer wires, collectively contributing to achieving low parasitic capacitance and low resistance, thereby enhancing the electrical performance of the device in various aspects.

The research team evaluated the speed of the new architecture and compared it with two of the most advanced memory technologies, DDR5 and HBM2E. Researchers claim that BBCube 3D could potentially achieve a bandwidth of 1.6 terabytes per second, which is 30 times higher than DDR5 and 4 times higher than HBM2E.

Furthermore, due to features like low thermal resistance and low impedance in BBCube, potential thermal management and power issues associated with 3D integration could be mitigated. The new technology significantly improves bandwidth while consuming only 1/20 and 1/5 of the bit access energy compared to DDR5 and HBM2E, respectively.

• Conclusion

The evolution of DRAM technology from 1D to 2D and now to the diverse structures of 3D has offered the industry various solutions to address its challenges. However, optimizing and improving manufacturing costs, durability, and reliability remain significant challenges in advancing 3D DRAM technology. Due to the difficulties in developing new materials and physical limitations, the commercialization of 3D DRAM still requires some time.

Based on the current research progress, the industry is actively engaged in the development of 3D DRAM, which are still in the early stages. According to industry insiders, it is predicted that 3D DRAM will begin to emerge around 2025, with actual mass production becoming feasible after 2030.

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(Photo credit: Samsung)