As TSMC’s earnings call approaches on April 18th, according to a source cited in a report from Commercial Times, it has predicted a downturn in the smartphone industry as it enters a slow season. However, TSMC is reportedly benefiting from AI demand, bolstering its operations through HPC (High-Performance Computing). Additionally, the increasing revenue share from the 3nm process is expected to contribute positively to performance in the second quarter.

TSMC has issued updates for three consecutive days, indicating that the overall recovery rate of its fabs has exceeded 80%. They reiterated their annual performance outlook from January’s earnings call, forecasting revenue growth in the low-to-mid twenties percentage range for the full year. Notably, in the fourth quarter of last year, the revenue share from high-performance computing matched that of smartphones, both reaching 43%, serving as dual engines for operational growth.

The same report, citing sources, indicates that TSMC’s advanced process technology and yield rates lead the industry, making it the primary foundry choice for most global customers.

Based on overall market share, TrendForce’s latest report reveals that in 2023, global foundry revenues hit US$117.47 billion, with TSMC capturing a dominant 60% share. This figure is expected to climb to around $131.65 billion in 2024, increasing TSMC’s share to 62%. It is also estimated in the report from Commercial Times that TSMC holds a market share of approximately 70-80% in 5nm technology, and this is expected to exceed 90% for 3nm, covering nearly all major players in the market.

TSMC has also emphasized that besides traditional smartphone applications, High-Performance Computing (HPC) is becoming an increasingly important application for their advanced processes. This means that even during the second quarter when demand for smartphone chips is typically lower, it will be supported by HPC demand.

The current major AI accelerators such as NVIDIA’s A100 and H100 GPUs, AMD’s Instinct MI250 and MI300, are all manufactured utilizing TSMC’s 7nm or 5nm nodes, highlighting TSMC’s critical position in the AI industry. Reportedly, as demand for AI-based Generative AI (AIGC) continues to rise, TSMC’s production volume is also expected to increase accordingly.

According to the same report citing sources, TSMC’s utilization rate for its 3nm production remains high and unaffected despite the impact of the recent earthquake on its facilities. TSMC has emphasized that key machines used for advanced processes, including all Extreme Ultraviolet (EUV), were undamaged.

However, in areas where the shaking was more severe, certain production lines are expected to require longer adjustments and calibration to restore automated production. TSMC is conducting a comprehensive review of the impact of this earthquake while maintaining close communication with its customers.

Furthermore, TSMC’s biggest challenge at the moment is how to catch up with customer expansion demands.

The most lacking capacity currently is in CoWoS production. Although TSMC maintains its stance of doubling capacity compared to 2023, market estimates cited in the report indicate that TSMC’s capacity is expected to increase from around 13,000 wafers to 30,000-35,000 wafers. This aligns with what founder Morris Chang described—AI chip demand in the future will no longer be in the tens or hundreds of thousands of wafers but will require the capacity of 3, 5, or even 10 fabs.

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(Photo credit: TSMC)

According to wccftech, Intel’s new GPUs will come in two models, namely Battlemage-G10 (abbreviated as BMG-G10) and Battlemage-G21 (abbreviated as BMG-G21).

These two new GPUs from Intel were revealed in an internal document. According to the document, the BMG-G10, targeted at enthusiasts, is a GPU with a TDP of less than 225W, while the BMG-G21 is designed as a mid-range performance product with a maximum TDP not exceeding 150W.

As for specific parameters and performance, the enthusiast-grade BMG-G10 is expected to be equipped with up to 64 Xe2 cores, directly competing with NVIDIA’s RTX 4070. On the other hand, the mid-range BMG-G21 aims at the RTX 4060, both continuing to utilize TSMC’s 4nm manufacturing process.

Therefore, previous rumors suggesting that Intel had canceled the development of BMG-G10 and only retained the BMG-G21 with 40 Xe2 cores appear to be untrue. Moreover, the core count of BMG-G10 is larger than initially reported at 56 Xe2 cores, indicating it is poised to deliver even higher performance.

Recently, per a report from Reuters, Intel, Qualcomm, Google, and other major tech companies are teaming up to challenge NVIDIA’s market dominance and make inroads into the AI software sector. They are expected to look to steer developers away from NVIDIA’s CUDA software platform, a parallel computing platform tailored for GPU acceleration.

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(Photo credit: Intel)

Recently, South Korean media Alphabiz reported that Samsung may exclusively supply 12-layer HBM3e to NVIDIA.

The report indicates NVIDIA is set to commence large-scale purchases of Samsung Electronics’ 12-layer HBM3e as early as September, who will exclusively provide the 12-layer HBM3e to NVIDIA.

NVIDIA CEO Jensen Huang, as per Alphabiz reported, left his signature “Jensen Approved” on a physical 12-layer HBM3e product from Samsung Electronics at GTC 2024, which seems to suggest NVIDIA’s recognition of Samsung’s HBM3e product.

HBM is characterized by its high bandwidth, high capacity, low latency, and low power consumption. With the surge in artificial intelligence (AI) industry, the acceleration of AI large-scale model applications has driven the continuous growth of demand in high-performance memory market.

According to TrendForce’s data, HBM market value accounted for approximately 8.4% of the overall DRAM industry in 2023, and this percentage is projected to expand to 20.1% by the end of 2024.

Senior Vice President Avril Wu notes that by the end of 2024, the DRAM industry is expected to allocate approximately 250K/m (14%) of total capacity to producing HBM TSV, with an estimated annual supply bit growth of around 260%.

HBM3e: Three Major Original Manufacturers Kick off Fierce Rivalry

Following the debut of the world’s first TSV HBM product in 2014, HBM memory technology has now iterated to HBM3e after nearly 10 years of development.

From the perspective of original manufacturers, competition in the HBM3e market primarily revolves around Micron, SK Hynix, and Samsung. It is reported that these three major manufacturers already provided 8-hi (24GB) samples in late July, mid-August, and early October 2023, respectively. It is worth noting that this year, they have kicked off fierce competition in the HBM3e market by introducing latest products.

On February 27th, Samsung announced the launch of its first 12-layer stacked HBM3e DRAM–HBM3e 12H, which marks Samsung’s largest-capacity HBM product to date, boasting a capacity of up to 36GB. Samsung stated that it has begun offering samples of the HBM3e 12H to customers and anticipates starting mass production in the second half of this year.

In early March, Micron announced that it had commenced mass production of its HBM3e solution. The company stated that the NVIDIA H200 Tensor Core GPU will adopt Micron’s 8-layer stacked HBM3e memory with 24GB capacity and shipments are set to begin in the second quarter of 2024.

On March 19th, SK Hynix announced the successful large-scale production of its new ultra-high-performance memory product, HBM3e, designed for AI applications. This achievement symbolizes the world’s first supply of DRAM’s highest-performance HBM3e in existence to customers.

A previous report from TrendForce has indicated that, starting in 2024, the market’s attention will shift from HBM3 to HBM3e, with expectations for a gradual ramp-up in production through the second half of the year, positioning HBM3e as the new mainstream in the HBM market.

TrendForce reports that SK hynix led the way with its HBM3e validation in the first quarter, closely followed by Micron, which plans to start distributing its HBM3e products toward the end of the first quarter, in alignment with NVIDIA’s planned H200 deployment by the end of the second quarter.

Samsung, slightly behind in sample submissions, is expected to complete its HBM3e validation by the end of the first quarter, with shipments rolling out in the second quarter. With Samsung having already made significant strides in HBM3 and its HBM3e validation expected to be completed soon, the company is poised to significantly narrow the market share gap with SK Hynix by the end of the year, reshaping the competitive dynamics in the HBM market.

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(Photo credit: SK Hynix)

Intel, Qualcomm, Google, and other tech giants are reportedly joining forces with over a hundred startups to challenge NVIDIA’s dominance in the market, as per a report from Reuters. Reportedly, their goal is to collectively penetrate the artificial intelligence (AI) software domain, guiding developers to migrate away from NVIDIA’s CUDA software platform.

NVIDIA’s CUDA is a parallel computing platform and programming model designed specifically to accelerate GPU computing. It allows GPU users to fully leverage their chip’s computational power in AI and other applications. As per a previous report from TrendForce, since 2006, NVIDIA has introduced the CUDA architecture, nearly ubiquitous in educational institutions. Thus, almost all AI engineers encounter CUDA during their academic tenure.

However, tech giants are now reportedly aiming to disrupt the current status quo. According to a report from Reuters on March 25th, Intel, Qualcomm, and Google are teaming up to challenge NVIDIA’s dominant position. They plan to provide alternative solutions for developers to reduce dependence on NVIDIA, encourage application migration to other platforms, and thereby break NVIDIA’s software monopoly and weaken its market influence.

The same report from Reuters further indicated that several tech companies have formed the “UXL Foundation,” named after the concept of “Unified Acceleration” (UXL), which aims to harness the power of acceleration computing using any hardware.

The project plans to leverage Intel’s oneAPI technology to develop software and tools supporting multiple AI accelerator chips. The goal is to reduce the technical barriers developers face when dealing with different hardware platforms, streamline the development process, enhance efficiency, and accelerate innovation and application of AI technology.

Vinesh Sukumar, Head of AI and Machine Learning Platform at Qualcomm, stated, “We’re actually showing developers how you migrate out from an NVIDIA platform.”

Bill Magro, Head of High-Performance Computing at Google, expressed, “It’s about specifically – in the context of machine learning frameworks – how do we create an open ecosystem, and promote productivity and choice in hardware.” The foundation is said to aim to finalize technical specifications in the first half of this year and strives to refine technical details by the end of the year.

However, CUDA software has established a solid foundation in the AI field, making it unlikely to be shaken overnight. Jay Goldberg, CEO of financial and strategic advisory firm D2D Advisory, believes that CUDA’s importance lies not only in its software capabilities but also in its 15-year history of usage. A vast amount of code has been built around it, deeply ingraining CUDA in numerous AI and high-performance computing projects. Changing this status quo would require overcoming significant inertia and dependency.

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(Photo credit: NVIDIA)

As the demand for AI is becoming urgent, according to industry sources cited by the ChinaTimes News, TSMC’s Fab20 P1 plant in Hsinchu’s Baoshan area will undergo equipment installation engineering in April to warm up for mass production of the GAA (gate-all-around) architecture.

Reportedly, it is expected that Baoshan P1, P2, and the three fabs scheduled for advanced process production in Kaohsiung will all commence mass production in 2025, attracting customers such as Apple, NVIDIA, AMD, and Qualcomm to compete for production capacity.

Regarding this rumor, TSMC declined to comment.

Per the industry sources cited by the same report, whether wafer manufacturing is profitable is depending on the yield after mass production. The key lies in the speed at which the yield improves; the longer it takes and the higher the cost, the more challenging it becomes.

As per the same report, TSMC is said to be accelerating its entry into the 2-nanometer realm in April, aiming to shorten the time required for yield improvement in advanced processes. This move not only poses a continuous threat to Samsung and Intel but also widens TSMC’s leading edge.

Industry sources cited by the ChinaTimes’ report have revealed that TSMC has prepared for first tool-in at P1, with trial production expected in the fourth quarter this year and mass production in the second quarter of next year. Equipment manufacturers indicate that they have already deployed personnel and conducted preparatory training in response to TSMC’s customized demands.

As a new milestone in chip manufacturing processes, the 2-nanometer node will provide higher performance and lower power consumption. It adopts Nanosheet technology structure and further develops backside power rail technology. TSMC believes that the 2-nanometer node will enable it to maintain its technological leadership and seize the growth opportunities in AI.

In fact, the cost of producing 2-nanometer chips is exceptionally high. Per the report citing sources, compared to the 3-nanometer node, costs are expected to increase by 50%, with the per-wafer cost reaching USD 30,000. Therefore, the initial adopters are expected to be smartphone chip clients, notably Apple.

Previously, per a report from the media outlet wccftech, Apple’s iPhone, Mac, iPad, and other devices will be the first users of TSMC’s 2nm process. Apple will leverage TSMC’s 2nm process technology to enhance chip performance and reduce power consumption. This advancement is expected to result in longer battery life for future Apple products, such as the iPhone and MacBook.

Unlike with the 3-nanometer node, the complexity of the design means customers must start collaborating with TSMC earlier in the development process. Market speculations suggest that many clients such as MediaTek, Qualcomm, AMD, and NVIDIA have already begun cooperation. TSMC’s earnings call also emphasized that the number of customers for N2 is higher than that for N3 at the same stage of development.

The Fab 20 facility is expected to begin receiving related equipment for 2nm production as early as April, with plans to transition to GAA (Gate-All-Around) technology from FinFET for 2nm mass production by 2025.

The competition in the development of 2-nanometer technology is fierce. ASML plans to produce 10 2-nanometer EUV lithography machines this year, with Intel already reserving 6 of them. Additionally, Japan has mobilized its national efforts to establish Rapidus Semiconductor Manufacturing, which also aims to compete in the 2-nanometer process.

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