The surging global demand for AI chips is straining advanced packaging capacity, driving a sharp focus on fan-out panel-level packaging (FOPLP) within Taiwan’s semiconductor industry. According to a report by Commercial Times, major packaging and testing firms such as ASE and Powertech, alongside equipment manufacturers like Gudeng, GPTC, E&R Engineering, Mirle, and analysis firm MAtek, are investing heavily in FOPLP technology.

The rapid development and expanding applications of AI chips have intensified the need for higher chip performance, smaller sizes, better heat dissipation, and lower costs. As emerging applications such as 5G, AIoT, and automotive chips continue to grow, the demand for high-performance, high-power semiconductors has surged. FOPLP technology, which enhances performance while significantly cutting costs and addressing thermal and signal integration issues, is emerging as a key trend in the market.

ASE has been working on panel-level packaging for several years. The company expects its panel-level packaging equipment to be in place by the second quarter of 2025, maintaining a technological edge. On October 2, ASE announced a nearly NT$8 billion purchase of equipment by its subsidiary, SPIL, from companies including Advantest.

Powertech has already moved into wafer-level fan-out packaging and is now shifting toward panel-level fan-out packaging. The company claims that the new technology can increase chip area output by two to three times. It has dedicated its Hsinchu plant to panel-level fan-out packaging and TSV CIS, positioning itself for future growth opportunities.

Equipment manufacturers are also seeking to capitalize on this trend. GPTC, a supplier to major foundries for InFO packaging, is expected to benefit from future FOPLP opportunities due to the similar nature of its equipment. Gudeng Precision is developing panel-level packaging transport boxes, with mass production expected in 2025.

FOPLP combined with TGV drilling is seen as the key to this technology. Analysts cited by Commercial Times highlight that FOPLP+TGV enables higher area utilization and unit capacity, which effectively reduces heterogeneous packaging costs.

E&R Engineering is focusing on drilling, testing, and cutting equipment for glass substrates, primarily supplying panel manufacturers in Taiwan and outsourced assembly and testing providers in Southeast Asia. Mirle has targeted glass substrate transport equipment, while MAtek is leading the market in glass substrate inspection technology.

(Photo credit: ASE)

With the surge in new applications like AI, advanced packaging remains a hot topic, particularly with FOPLP (Fan-Out Panel Level Packaging) technology gaining renewed attention. According to sources cited by a report from MoneyDJ, leading semiconductor foundry TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

TSMC introduced the FOWLP (Fan-Out Wafer Level Packaging) technology named InFO (Integrated Fan-Out) in 2016, first used in the iPhone 7’s A10 processor. Subsequently, assembly and testing facilities actively promoted FOPLP solutions, looking to attract customers with lower production costs, yet faced ongoing technical challenges. Therefore, current terminal applications remain within mature processes, such as PMIC (Power Management IC) products.

However, per the sources cited by the same report, TSMC’s move to transition advanced packaging technology from wafer level to panel level is more than just talk—it’s becoming a reality. It is reported that TSMC is planning to use rectangular substrates measuring 515mm by 510mm, with a dedicated team already conducting research and planning to establish a mini line.

The source further mentioned that, TSMC’s development of FOPLP can be seen as a rectangular version of InFO, offering advantages such as lower unit costs and larger package sizes.

This advancement could further integrate other technologies on TSMC’s 3D fabric platform, paving the way for 2.5D/3D advanced packaging solutions to serve high-end product applications. This approach could be regarded similar to a rectangular CoWoS, currently targeted at the AI GPU sector with NVIDIA as a customer. If progress continues smoothly, these developments could potentially debut between 2026 and 2027.

On the AMD front, it is understood that their initial partners for FOPLP are ASE Technology and PowerTech Technologies, with potential applications in PC or gaming console chips. Reportedly, it’s suggested that previous packaging methods for PCs and gaming consoles primarily used FC-BGA, but upcoming new products may potentially upgrade to CoWoS level.

Sources cited by the report note that in the early stages of FOPLP, players like PowerTech Technologies, Innolux, and ASE Technology faced challenges and intermittent demand. To allocate resources effectively, equipment suppliers have been conservative in their investments in related fields, focusing mainly on adjusting specifications to meet customer demands. With TSMC now officially joining, equipment suppliers are shifting to a more proactive stance in preparation for upcoming developments.

In summary, the development of the FOPLP ecosystem hinges largely on TSMC’s role. TSMC is expected to maintain leadership in the high-end segment, while packaging and testing firms will cater to the mid-to-high-end markets. Semiconductor experts believe that in the realm of high-speed computing, CoWoS will remain mainstream for the next 3 to 5 years, with advanced 3D packaging like SoIC gaining prominence in high-end applications, solidifying TSMC’s position as a key player.

For packaging and testing companies, the key lies in product upgrades that offer cost-effectiveness. The success of FOPLP as the next generation of advanced packaging hinges on how chip manufacturers position their products, address yield issues related to warpage, and ensure overall performance and pricing that justify customer investment.

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(Photo credit: TSMC)

To alleviate the capacity constraints of CoWoS advanced packaging, NVIDIA is reportedly planning to accelerate the introduction of its GB200, into panel-level fan-out packaging. According to a report from Economic Daily News, originally scheduled for 2026, this shift has been moved up to 2025, sparking opportunities in the panel-level fan-out packaging sector.

Taiwanese companies like Powertech Technology Inc. (PTI) and AU Optronics (AUO) are said to have prepared with the necessary capabilities, expected to seize this market opportunity.

The sources cited by the report from Economic Daily News explain that fan-out packaging has two branches: wafer-level fan-out packaging (FOWLP) and panel-level fan-out packaging (FOPLP). Among Taiwanese packaging and testing companies, PTI is reportedly the fastest in deploying panel-level fan-out packaging.

To capture the high-end logic chip packaging market, PTI has fully dedicated its Hsinchu Plant 3 to panel-level fan-out packaging and TSV CIS (CMOS image sensors) technologies, emphasizing that fan-out packaging can achieve heterogeneous integration of ICs.

PTI previously expressed optimism about the opportunities presented by the era of panel-level fan-out packaging, noting that it can produce chip areas two to three times larger than wafer-level fan-out packaging.

Innolux, a major panel manufacturer, is also optimistic, forecasting that 2024 will be the advanced packaging mass production inaugural year for the group. The first phase capacity of its fan-out panel-level packaging (FOPLP) production line has already been fully booked, with mass production and shipments scheduled to begin in the third quarter of this year.

Chairman of Innolux Jim Hung emphasized that advanced packaging technology (PLP) connects chips through redistribution layers (RDL), meeting the requirements for high reliability, high power output, and high-quality packaging products. This technology has secured process and reliability certifications from top-tier customers, and its yield rates have been well received, with mass production set to commence this year.

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(Photo credit: NVIDIA)