Converting LCD panel factories into semiconductor bases seems to emerge as one of the latest trends in the semiconductor industry. According to a report by Nikkei News, Intel plans to utilize Sharp’s LCD panel factory in Japan, and collaborate with Japanese companies to develop semiconductor production technology.

Intel will reportedly collaborate with 14 Japanese suppliers, including Omron, Resonac, and Murata Machinery, to develop “backend process” technologies responsible for semiconductor assembly. They plan to use Sharp’s LCD panel factory as a research and development site, as the target locations potentially being Sharp’s Kameyama plant or Mie plant.

For display manufacturers, their ability to effectively control contaminants in the manufacturing environment directly impacts the fluctuations in yield. LCD panels, like semiconductors, suffer from decreased yield if even minute dust or particles are introduced during the manufacturing process. Thus, LCD panel factories are equipped with clean rooms designed to minimize dust and particles, making them suitable for both production and semiconductor research and development.

The report also stated that in addition to Intel, Rapidus, which aims to mass-produce cutting-edge 2-nanometer chips, and Mitsubishi Electric will also utilize existing LCD factories for semiconductor research and development.

In mid-May, per another report by Nikkei, Sharp decided that Sakai Display Products (SDP), its 10th generation panel factory, which produces large-sized LCD panels for TVs, would cease production by the end of September. Additionally, production of medium and small-sized LCD panels would be reduced. Instead, the company intends to seek collaboration with other companies and optimize its factories to improve profitability.

According to the report, currently, Sharp produces medium and small-sized panels at its Kameyama, Mie, and Hakusan factories. Daily production at Kameyama’s second factory is expected to decrease from 2,000 panels to 1,500, while production at Mie’s third factory will drop from 2,280 panels to 1,100, a 52% reduction, while the OLED production line at the Tenjiku factory will be closed.

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(Photo credit: Intel)

On May 16, Japanese foundry startup Rapidus announced the signing of a Memorandum of Understanding (MoU) with American RISC-V architecture chip design company, Esperanto. The two sides will collaborate on the research and development of AI semiconductors for data centers, aiming to jointly develop low-power AI chips.

Currently, according to a report from DRAMeXchange, despite the gradual ease of GPU shortage, power supply has become another bottleneck in the course of the AI development.

Industry sources cited in the report have pointed out that CPU and GPU have played a critical role in fostering the prosperity of the AI market. However, the increasing power consumption of the latest chips is causing a recent crisis. For instance, it is expected that by 2027, the energy consumed by generative AI processing will account for nearly 80% of the total electricity consumption of data centers in the United States.

Data center is a major engine to drive the growth of electricity demand. With the advent of the AI era, represented by generative AI, the power required for high-performance computing chips continuously increases, which in turn raises the electricity consumption of data centers.

Esperanto has been committed to designing large-scale parallel, high-performance, and energy-efficient computing solutions. Previously, it launched the ET-SOC-1-based RISC-V architecture many-core AI/HPC acceleration chip, built on TSMC’s 7nm process.

Rapidus is a wafer foundry founded in August 2022 with joint investments from eight Japanese companies, including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND flash giant Kioxia, and Mitsubishi UFJ. Its first factory, “IIM-1,” based in Chitose, Hokkaido, already broke ground in September 2023 and is expected to start running trial production lines in April 2025 and install EUV lithography machines. Rapidus aims to mass-produce the most advanced logic chips below 2nm by 2027.

The initial focus of the cooperation between Rapidus and Esperanto is to enable future semiconductor designers to develop more energy-efficient solutions for AI inference and high-performance computing workloads in data centers and enterprise edge applications. This will help mitigate the unsustainable growth of energy consumption across global data centers.

In 2022, data center, AI, and cryptocurrency consumed about 460 TWh of electricity worldwide in total, comprising 2% of the overall global demand. The International Energy Agency (IEA) predicts that, influenced by factors such as generative AI, global data center power demand could rise to about 1,000 TWh in 2026, roughly equivalent to the entire electricity consumption in Japan.

IEA states that updated regulations and technological improvements, including energy efficiency, are of great significance to curb the surge in data center energy consumption.

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• [News] Rapidus Focuses on Small Clients, Diversifies into Japan to Mitigate US Geopolitical Risks
• [News] Rapidus, the First 2nm Client, to Manufacture AI Chips for Tenstorrent

(Photo credit: Rapidus)

Henri Richard, head of Rapidus Design Solutions, the US subsidiary of Japan’s semiconductor foundry startup Rapidus, and former Chief Marketing Officer at processor giant AMD, indicates that Rapidus aims to position itself as a filler of market gaps during the interview with global media The Register.

Rapidus Design Solutions, established by Rapidus in this month, is expected to bolster ties with US semiconductor design companies and wafer manufacturing technology providers like IBM. Henri Richard reportedly notes that the AI boom is boosting the advanced semiconductor foundry market, albeit with understated demand and ongoing capacity constraints. Thus, in this market trend, he asserts that even if these technologies don’t necessarily confer a competitive edge, the limitations in capacity alone should suffice to ensure Rapidus’ success.

Established in August 2022, Rapidus was jointly founded by eight Japanese companies, including Toyota, Sony, NTT, NEC, Softbank, Denso, Kioxia (formerly Toshiba Memory Corporation), and Mitsubishi UFJ, who invested collectively in its establishment. As per Rapidus’ plan, they aim to commence mass production of 2-nanometer process technology in 2027, significantly lagging behind major global players like TSMC, Intel, and Samsung.

TSMC and Samsung previously planned to mass-produce 2nm chips in 2025, while Intel is anticipated to be the first to achieve commercialization of 2nm chips. Industry sources cited by the The Register’s report also view this timing as unfavorable for Rapidus.

However, Henri Richard believes that the semiconductor process technology has reached a turning point. Assessing the success of suppliers solely based on production timelines is narrow-minded; competitiveness stems from various factors beyond production schedules.

Based on these factors, Rapidus positions itself as a fill-in player in the advanced manufacturing market, targeting small AI chip design companies as its primary market. While competitors focus on serving large clients, Rapidus aims to win over these smaller clients by offering comprehensive support services. By serving numerous small chip design companies, Rapidus can better understand the specific needs of AI chip users, rather than insisting on the latest process technology for all chips.

Henri Richard emphasizes that Rapidus itself has limited scale and cannot initially serve too many clients simultaneously. It is expected that Rapidus’s initial client base will not exceed 6 companies, allowing them to accumulate experience and capabilities.

Although there are geopolitical issues currently, establishing facilities in the US is not on Rapidus’s immediate agenda. Meanwhile, Japan represents a relatively favorable geographic location for Rapidus, offering clients a risk-diversification option.

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• [News] Global Acceleration in the Construction of 2nm Wafer Plants
• [News] Rapidus, the First 2nm Client, to Manufacture AI Chips for Tenstorrent

(Photo credit: Rapidus)

Amid the overwhelming wave of Artificial Intelligence, the importance of advanced process chips is becoming increasingly prominent. Currently, the 3nm process is the most advanced node in the industry. Meanwhile, manufacturers such as TSMC, Samsung, Intel, and Rapidus are actively promoting the construction of 2nm wafer fabs. TSMC and Samsung previously planned to mass-produce 2nm chips in 2025, while Rapidus to begin trial production in 2025.

2nm Wafer Fabs to Complete Construction as Soon as this Year?

Recently, the Semiconductor Equipment and Materials International (SEMI) announced that it is expected that both TSMC and Intel will potentially complete the construction of 2nm wafer fabs by the end of this year.

Intel is anticipated to be the first to achieve commercialization of 2nm chips. The Intel PC CPU Arrow Lake product will utilize the 2nm process node. TSMC’s 2nm process is expected to be applied in Apple’s iPhone AP chips. Subsequently, TSMC’s 2nm capacity will soar up.

According to a report from Commercial Times the installation of equipment for TSMC’s 2nm process is accelerating. TSMC’s Fab20 P1 plant in Hsinchu, Baoshan is scheduled to install equipment in April this year, with pilot production expected to commence in 2H24 and small-scale production in 2Q25.

As for Intel, ASML already delivered the world’s first High Numerical Aperture (NA) EUV EXE:5200 to Intel in late 2023, supporting the latter in producing 2nm chips. Later, Intel kicked-start the calibration of lithography machine, which has been well on track.

Samsung and Rapidus all Set to Move

In terms of Samsung, its previously announced technology roadmap indicates that it will first mass-produce 2nm process chips for mobile terminals starting in 2025, followed by high-performance computing (HPC) products in 2026. It plans to expand to automotive chips by 2027.

Rapidus is setting up a 2nm chip fab in Chitose City, Hokkaido, Japan. Its pilot production line is scheduled to start operation in April 2025, aiming to commence mass production in 2027.

Recently, it’s reported that in order to promote the development of advanced wafer fabs in Japan, several Japanese manufacturers will supply products to Rapidus. Among them, Dai Nippon Printing (DNP) will begin mass production of masks for 2nm chips at its Fukuoka plant and other operations in Japan in 2027, which will be provided to Rapidus.

In addition to DNP, Japanese company TOPPAN Holdings is also collaborating with IBM to develop masks for 2nm chips and achieve mass production by 2026, and Rapidus is reportedly the purchaser. Moreover, companies like Tokyo Ohka Kogyo (TOK), JSR, Shin-Etsu Chemical are also expected to be the suppliers of Rapidus.

1nm Chip Plans Brought to Light

Following 2nm, 1nm chip will be the next target for wafer fabs. In light of manufacturers’ plans, the industry is expected to see mass production of 1nm-level chips from 2027 to 2030.

TSMC plans to reach the A14 node (1.4nm) in 2027 and the A10 node (1nm) in 2030. Recent reports from Economic Daily News indicated that TSMC intends to establish a factory in the Science Park of Taibao City, Chiayi County in central Taiwan to produce 1nm chips.

Samsung anticipates to launch the 1.4nm process by late 2027. It is reported that Samsung’s SF1.4 (1.4 nm) process can increase the number of nanosheets from 3 to 4, which is expected to significantly improve performance and power consumption.

Intel’s latest foundry roadmap shows that the Intel 14A (1.4nm-level) node will put into production in 2026, and Intel 10A (1nm-level) will start development or production in late 2027.

Recently, IC design company Marvell announced an expansion of its long-term partnership with TSMC to include 2-nanometer technology. They will collaborate on developing the industry’s first 2-nanometer semiconductor production platform optimized for accelerating infrastructure.

Currently, the most advanced production technology in the industry is the 3-nanometer process, manufactured by Samsung Electronics and TSMC. With Intel securing the first ASML lithography machine and updating its latest manufacturing roadmap, and with the increasing collaboration between Rapidus and IBM, the competition for the 2-nanometer advanced process has significantly expanded to include TSMC, Intel, Samsung and  Rapidus.

• Marvell

According to Marvell’s press release, it has stated that Marvell has transitioned from a follower to a leader in integrating advanced node technology into silicon infrastructure.

Marvell first bringing advanced node technology to infrastructure silicon with its 5nm platform, followed by the release of several 5-nanometer designs and the profolio of the first silicon infrastructure product lineup based on TSMC’s 3-nanometer process.

“Tomorrow’s artificial intelligence workloads will require significant and substantial gains in performance, power, area, and transistor density. The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure capable of delivering on the promise of AI,” said Sandeep Bharathi, chief development officer at Marvell.

• TSMC

TSMC commenced mass production of its 3-nanometer process in 2022, with profitability realized starting from the third quarter of 2023. By the fourth quarter of 2023, the 3-nanometer process contributed to 15% of wafer revenue, and its revenue share has been steadily increasing.

According to TrendForce, the foundry market is expected to grow by 7% in 2024, largely attributed to TSMC’s ramp-up of its 3-nanometer process. This has further increased TSMC’s market share.

During the earnings call in the fourth quarter of 2023, TSMC announced that its 2-nanometer process (N2) would utilize Nanosheet transistor structures. It is anticipated that N2 will commence mass production in 2025, leading the industry in terms of density and energy efficiency.

The N2 backside power delivery solution is slated for release in the latter half of 2025 and is expected to enter mass production in 2026, primarily targeting the High-Performance Computing (HPC) sector.

Furthermore, due to the current high demand for 2-nanometer processes from all AI innovators worldwide surpassing that for 3-nanometer processes, almost all AI innovators are collaborating with TSMC on 2-nanometer process technology. The main applications are primarily focused on high-performance computing (HPC) and smartphones.

Consequently, TSMC has announced plans to expand its production capacity for 2-nanometer processes. Originally, two 2-nanometer fabs were planned for the Kaohsiung facility, but now consideration is being given to constructing a third 2-nanometer fab.

• Samsung

Samsung commenced mass production of its 3-nanometer process in June 2022. According to the latest industry reports, Samsung has developed a “second-generation 3-nanometer” process, renamed as “2-nanometer”, with plans for mass production before the end of this year.

At the 2023 Samsung Foundry Forum, Samsung Electronics unveiled the latest roadmap for its 2-nanometer process. Samsung Electronics President and Head of Foundry Business, Siyoung Choi, disclosed that Samsung will first mass-produce 2-nanometer chips for mobile terminals starting from 2025. Subsequently, in 2026, the technology will be applied to high-performance computing (HPC) products, followed by expansion to automotive chips by 2027.

Unlike TSMC, which opted for Gate-All-Around (GAA) structure at the outset of its 2-nanometer process, Samsung has been utilizing GAA structure since its 3-nanometer process. This suggests that Samsung may have more experience in new structures compared to TSMC, thus giving Samsung an advantage in its 2-nanometer node.

In the past, when Samsung Electronics transitioned from 7-nanometer to 5-nanometer process technology in 2020, the second generation 7-nanometer process technology was renamed as 5-nanometer process technology.

Samsung Electronics’ 7-nanometer process technology became the world’s first to use Extreme Ultraviolet (EUV) lithography in 2019, making it more stable and enabling the company to further shrink transistor sizes. This was also the reason for renaming the second generation 7-nanometer process to 5-nanometer process at that time.

A report from the Business Korea has indicated that Samsung Electronics recently secured an order from the Japanese AI startup Preferred Networks (PFN) to produce semiconductors based on the 2-nanometer process.

It is reported that PFN has been collaborating with TSMC since 2016, but this year, it has decided to produce the next generation of AI chips at Samsung’s 2-nanometer node. According to the agreement, Samsung will utilize its latest 2-nanometer chip fab technology to manufacture AI accelerators and other AI chips for PFN.

• Intel

As per Intel’s previously announced plans, the company aims to catch up with and surpass TSMC by 2024 or 2025. At this year’s “Direct Connect” conference hosted by Intel Foundry Services, the company unveiled its latest technological roadmap.

Intel has reported that its primary product, Clearwater Forest, which is under the 18A process, has been completed and is set for production in 2025. Intel’s 18A process is often compared with TSMC’s N2 (2-nanometer) and N3P (3-nanometer) processes in terms of performance, with each company advocating for its own advantages.

Intel CEO Pat Gelsinger emphasizes that both 18A and N2 utilize GAA transistors (RibbonFET), but the 1.8-nanometer node will adopt BSPND, a backside power delivery technology that optimizes power and clock. TSMC, on the other hand, believes that its N3P (3-nanometer) technology will rival Intel’s 18A in power consumption, performance, and area (PPA), while its N2 (2-nanometer) will surpass it in all aspects.

Additionally, Intel’s 20A manufacturing technology is reportedly scheduled for launch in 2024, introducing two technologies: RibbonFET surround gate transistors and backside power delivery network (BSPDN). These aim to achieve higher performance, lower power consumption, and increased transistor density.

Meanwhile, Intel’s 18A production node aims to further refine the innovations of 20A and provide additional PPA improvements from late 2024 to early 2025. Per Intel’s statements regarding its fab processes, its 2-nanometer technology is expected to be the earliest to debut.

Of particular note, Intel announced for the first time at the conference the development of 14A (1.4nm) and its evolutionary version, 14A-E. Intel’s 14A process is the industry’s first node to utilize ASML High-NA EUV lithography tools, making Intel the first company in the industry to acquire cutting-edge High-NA tools. Intel expects to develop 14A by 2027.

• Rapidus

In addition to the aforementioned semiconductor foundries, a Japanese company, Rapidus, is worth noting as well. Established in August 2022, Rapidus was jointly founded by eight Japanese companies including Toyota, Sony, NTT, NEC, SoftBank, Denso, NAND Flash giant Kioxia, and Mitsubishi UFJ.

On January 22nd of 2024, Rapidus President Junichi Koike announced during a press conference that construction of the Rapidus 2-nanometer chip fab in Japan is progressing smoothly, and the trial production line is scheduled to commence operations in April 2025 as planned. Additionally, there are plans for the construction of a second and third facility in the future.

In September of last year, Rapidus began construction of Japan’s first logic chip fab, “IIM-1,” in Chitose City, Hokkaido, capable of producing chips below 2 nanometers. It is reported that the fab is expected to be completed by December of this year.

Previously, Rapidus signed a collaboration agreement with IBM to develop technology based on IBM’s 2-nanometer process. IBM had already introduced the world’s first 2-nanometer process chip back in 2021. Similarly, IBM’s 2-nanometer process also utilizes GAA (Gate-All-Around) structure. This partnership provides Rapidus with the technical support necessary for advanced process development.

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• [News]The 2nm Semiconductor Foundry Race Between TSMC, Samsung, Rapidus Begins with an Equipment Battle

(Photo credit: TSMC)