The growing importance of advanced processes in wafer foundries is evident, propelled by innovations like AI and high-performance computing. While 3nm chips have entered the consumer market, efforts are underway in wafer foundries to advance to 2nm chips. Recent reports suggest progress in 1nm chips, further fueling the competition among wafer foundries.

2nm Chips: Unveiling in 2025

Anticipated by 2025, the race for 2nm chips is in full swing, with major players like TSMC, Samsung, and Rapidus actively pursuing mass production. TSMC plans to implement GAAFET transistors in its 2nm process by 2025, offering a 15% speed boost and up to a 30% reduction in power consumption compared to N3E, all while increasing chip density by over 15%.

Samsung is on a similar trajectory, planning to unveil its 2nm process by the end of 2025. As report by media in October, Samsung Foundry, said on Semiconductor Expo 2023 in South Korea, has already initiated discussions with major clients, expecting decisions in upcoming future.

Rapidus aims for trial production of 2nm chips in 2025, scaling up to mass production by 2027. Reports in September indicated that ASML plans to establish a technical support hub in Hokkaido, Japan in 2024. Approximately 50 engineers will be dispatched to Rapidus’ ongoing construction site for the 2nm plant, assisting in the setup of EUV lithography equipment on the trial production line, and providing support for factory activation, maintenance, and inspections.

When will 1nm chip arrive?

Apart from 2nm, the industry’s attention turns to 1nm-level chips. According to industry plans, mass production of 1nm-level chips is expected between 2027 and 2030.

Nikkei recently reveals collaboration between Japanese chipmaker Rapidus, Tokyo University, and the French technological research organization Leti to develop foundational technology for 1nm IC design. Talent exchange and technical sharing are slated to begin in 2024, aiming to establish a supply system for indispensable 1nm chip products, crucial for enhancing auto driving and AI performance.

On the other hand, collaborations with IBM for 1nm products are also being considered. The computing performance of 1nm products, anticipated to become mainstream in the 2030s, is expected to surpass 2nm by 10-20%.

TSMC and Samsung are also eyeing 1nm chip development. TSMC’s initial plan to build a 1.4nm process wafer fab in Taiwan faced delays after abandoning the original site selection in October. Samsung aims to launch its 1.4nm process by the end of 2027, with improved performance and power consumption through an increased number of nanosheets per transistor, promising enhanced control over current flow and reduced power leakage.

(Image: TSMC)

According to a report by Bloomberg, Yoshihiro Seki, Secretary-General of the ruling Liberal Democratic Party and a member of the Japanese parliament, has announced that the government is planning to allocate an additional ¥900 billion for the construction of TSMC’s Fab 2 in Kumamoto, Japan. Furthermore, an extra ¥590 billion in subsidies will be provided to support the construction of a wafer fab by the Japanese semiconductor startup Rapidus.

Seki emphasized that subsidies usually cover about one-third of the total investment. With measures like training Japanese engineers and collaborative R&D with local companies, this subsidy could increase to potentially cover up to half of the investment. He also noted that the specific amount remains subject to change as the additional budget has not been finalized yet.

The Japanese government initiated the “Strategy for Semiconductors and the Digital Industry” in 2021 to address economic risks and prepare for the wave of digitalization. At that time, they already provided ¥476 billion in subsidies for TSMC’s Kumamoto 1st Fab. The current subsidy marks an expansion of these efforts.

The local government Kumamoto is eagerly anticipating TSMC’s presence. Ikuo Kabashima, the Governor of Kumamoto Prefecture, recently proposed “New Airport Concept Next Stage” that envisions using the airport as a hub for semiconductor imports and exports over the next decade. This plan aims to stimulate the clustering of semiconductor-related industries and contribute to regional development centered around Kumamoto.

Moreover, the Japanese government has pledged to provide ¥330 billion in funding to enable Rapidus to construct a 2nm wafer fab in Hokkaido. These substantial subsidies underscore the Japanese government’s commitment to these semiconductor projects.

In response to the Japanese government’s additional subsidies, Tetsuro Higashi, Chairman of Rapidus, stated in an interview with Jiji Press on the 24th that apart from the new factory being built in Chitose, Hokkaido, “We also plan to construct second and third factories, and they will also be situated in Chitose, Hokkaido.” Rapidus’s 2nm chip R&D/production facility, Chitose Fab IIM-1, located in the Chitose Meimeimei World industrial park in Chitose, Hokkaido, commenced construction in September. The trial production line is expected to start in April 2025, with mass production slated to begin in 2027.

TSMC is in the process of constructing a semiconductor factory in Kikuyo-cho, Kumamoto Prefecture, Kyushu, Japan (referred to as Plant 1). Production is expected to commence in December 2024. Besides this facility, TSMC has shown interest in establishing a second plant in Japan (referred to as Plant 2). According to Japanese reports, the government is considering providing TSMC with a substantial subsidy of up to 900 billion Japanese Yen for Plant 2.

On October 4, during the Public-Private Partnership Forum on Increasing Domestic Investment led by Japanese Prime Minister Fumio Kishida, plans were announced for economic measures to be finalized within October. The Ministry of Economy, Trade, and Industry of Japan (METI) will request a budget of 3.4 trillion Japanese Yen to establish three funds supporting semiconductor production and research and development. These funds are the ” Research and Development Project of the Enhanced Infrastructures for Post-5G Information and Communication Systems,” the “Specified Semiconductor Funding Program,” and the “Ensuring Stable Supply Support Fund.”

As reported by Asahi Shimbun, sources suggest that the METI deems it necessary to grant 900 billion Japanese Yen in subsidies for TSMC’s proposed Plant 2, nearly 600 billion Japanese Yen for the “Rapidus” national team aiming to produce next-gen semiconductor chips domestically, and 700 billion Japanese Yen for traditional chips like Sony CMOS image sensors.

The Japanese government will allocate the required funds for these economic measures in the 2023 fiscal year supplementary budget. If the METI’s budget request is approved, the budget for semiconductor-elated activities in the 2023 fiscal year supplementary budget (3.4 trillion Japanese Yen) will be 2.6 times higher than that in the 2022 fiscal year supplementary budget (1.3 trillion Japanese Yen).

The Kishida administration also announced plans to ease land restrictions for crucial manufacturing facilities such as semiconductor plants during the forum. As early as December, local governments will be able to issue development permits for agricultural land, forests, and other areas.

Before that, local governments could only grant permits for industries related to food logistics, data centers, and plant facilities. Now, this is being expanded to include vital strategic materials. Furthermore, changing the land category from agricultural land often required approvals from multiple government departments, a process that could take more than a year. In the future, these procedures are expected to be shortened to around four months.

(Image: Briáxis F. Mendes (孟必思), CC BY-SA 4.0, via Wikimedia Commons)

While 2nm advanced semiconductor chips are yet to enter mass production, the battle for equipment among semiconductor foundries is already in full swing.

TSMC, Samsung, and Rapidus Make Their Moves

To ensure the smooth deployment of 2nm process technology, TSMC, Samsung, and Rapidus have all embarked on pursuits in the upstream equipment sector.

TSMC, on September 12th, announced its intention to acquire a 10% stake in IMS Nanofabrication, a subsidiary of Intel, for no more than $432.8 million. IMS specializes in the development and production of electron beam lithography machines, widely used in semiconductor manufacturing, optical component production, MEMS manufacturing, and more. Industry experts believe that TSMC’s acquisition of IMS will ensure the development of critical equipment technology and meet the supply requirements for the commercialization of 2nm.

On the other hand, Samsung previously acquired a 3% stake in ASML, still holding approximately 0.7% of ASML shares. Additionally, Samsung’s collaboration with ASML continues to deepen. Reports suggest that Samsung is preparing to secure production of the next-generation High-NA EUV lithography machine, with the prototype expected to be unveiled later this year and commercial availability in the following year.

As for the semiconductor newcomer, Rapidus, obtaining ASML’s support is essential, given that EUV is a vital technology for mass-producing chips below 5-7nm. The latest reports from Japanese media indicate that ASML will establish a technical support base in Hokkaido, Japan, in 2024 and dispatch about 50 engineers to assist in setting up EUV lithography equipment in Rapidus’ 2nm chip factory’s pilot production line, offering assistance in commissioning, maintenance, and inspection.

The development of the major manufacturers in 2nm will be revealed in 2025

Leading traditional semiconductor foundries TSMC and Samsung, along with the emerging player Rapidus, are all actively positioning themselves in the 2nm chip landscape. So, how are these three companies progressing?

TSMC is targeting the production of N2 technology by 2025. Reports from June indicated that TSMC is fully committed, initiating preliminary preparations for the trial production of 2nm chips. In July, the TSMC supply chain revealed that TSMC had informed equipment suppliers to begin deliveries of 2nm-related machinery starting in the third quarter of the following year. In September, media reports revealed that TSMC had formed a dedicated 2nm task force, aiming to achieve risk production next year and commence mass production by 2025.

In June, Samsung announced its latest foundry technology innovations and business strategies, unveiling detailed plans and performance levels for 2nm process mass production. They plan to apply the 2nm process to mobile applications by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively.

According to Rapidus’ plan, trial production of 2nm chips is set to begin in 2025, with mass production slated for 2027. In July, Rapidus President Atsuyoshi Koike stated that operating a trial production line in 2025 and commencing mass production in 2027 is an ambitious goal, but progress is on track. He noted that once the company’s 2nm process products go into mass production, their unit price will be ten times that of current Japanese-produced logic semiconductors.

With this timeline, it appears that the 2nm chips from these three semiconductor giants will first make their debut in 2025. At that time, the competition for advanced 2nm processes is expected to become even more intense.

(Photo credit: TSMC)

In the continued sluggish consumer electronics market and amidst the booming era of artificial intelligence, semiconductor manufacturers are actively targeting high-performance chips and intensifying the competition over the 2nm process node.

TSMC, Samsung, and the newcomer Rapidus are all actively positioning themselves in the 2nm chip race. Let’s take a look at the progress of these three enterprises.

TSMC: Roadmap for 3nm and 2nm Unveiled

TSMC believes that, at the same power level, the 2nm (N2) chip speed can increase by 15% compared to N3E, or reduce power consumption by 30%, with a density 1.15 times that of its predecessor.

TSMC’s current roadmap for the 3nm “family” includes N3, N3E, N3P, N3X, and N3 AE. N3 is the basic version, N3E is an improved version with further cost optimization, N3P offers enhanced performance, planned for production in the second half of 2024, N3X focuses on high-performance computing devices, and aims for mass production in 2025. N3 AE, designed for the automotive sector, boasts greater reliability and is expected to help customers shorten their product time-to-market by 2 to 3 years.

As for 2nm, TSMC foresees the N2 process to enter mass production in 2025. Media reports from June this year indicate that TSMC is fully committed and has already commenced pre-production work for 2nm chips. In July, the TSMC supply chain revealed that the company has informed equipment suppliers to start delivering 2nm-related machines in the third quarter of next year.

Samsung Electronics: 2nm Mass Production by 2025

In June this year, Samsung announced its latest foundry technology innovations and business strategies.

Embracing the AI era, Samsung’s semiconductor foundry plans to leverage GAA advanced process technology to provide robust support for AI applications. To achieve this, Samsung unveiled detailed plans and performance levels for 2nm process mass production. They aim to realize the application of 2nm process in the mobile sector by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively.

Samsung states that the 2nm process (SF2) offers a 12% performance improvement and 25% power efficiency increase over the 3nm process (SF3), with a 5% reduction in chip area.

Rapidus: 2nm Chip Making Progress

Established in November 2022, Rapidus gained significant attention as eight major Japanese companies, including Sony Group, Toyota Motor, SoftBank, Kioxia, Denso, NTT, NEC and MUFG jointly announced their investment in the company. Just a month after its founding, Rapidus forged a strategic partnership with IBM to jointly develop 2nm chip manufacturing technology.

According to Rapidus’ plans, 2nm chips are set to begin trial production in 2025, with mass production commencing in 2027.

[Update] Intel: Being Ambitious to Start Mass Production Of Its 20A Process in The First Half of 2024

Intel is making a vigorous stride into the semiconductor foundry market, setting its sights on rivals like TSMC and Samsung in the arena of advanced process technologies. Intel’s ambitious road map includes kick-starting mass production of its 20A process in the first half of 2024, followed by an 18A process rollout in 2H24. TrendForce points out, however, Intel has a number of significant hurdles to overcome:

Intel’s longstanding focus on manufacturing CPUs, GPUs, FPGAs, and associated I/O chipsets leaves it short of the specialized processes mastered by other foundries. Therefore, the potential success of Intel’s acquisition of Tower—a move to broaden its product line and market reach—is a matter of crucial importance.

Beyond financial segregation, the division of Intel’s actual manufacturing capabilities poses a pivotal challenge. It remains to be seen whether Intel can emulate the complete separation models like those of AMD/GlobalFoundries or Samsung LSI/Samsung Foundry, staying true to the foundry principle of not competing with clients. Adding complexity to the mix, Intel faces the potential exodus of orders from a key customer—its own design division.

(Photo credit: TSMC)