According to a report from Commercial Times, the construction at TSMC’s advanced packaging plant (P1) in the Chia-Yi Science Park has been halted due to the discovery of suspected historical artifacts. In response, TSMC has promptly initiated preparations for its second plant (P2). TSMC stated that they will comply with regulations from the relevant authorities regarding the suspected archaeological site found on the Chia-Yi facility grounds.

The total developed area of the Chia-Yi Science Park is approximately 88 hectares, with TSMC’s two advanced packaging plants occupying 20 hectares. This is nearly 40% larger than the 14.3 hectares of the Zhunan packaging and testing plant. The planned area for the P1 plant is about 12 hectares, initially slated for completion by the end of 2026 and mass production by 2028. The discovery of the archaeological site has led to the early initiation of the P2 plant, raising concerns about potential impacts on the advanced packaging capacity plans.

The Southern Taiwan Science Park Administration and the Cultural and Tourism Bureau of Chiayi County both stated on June 17 that, in accordance with the Cultural Heritage Preservation Act, they submitted the case to the Chiayi County Cultural and Tourism Bureau for cultural heritage review on June 7. The review committee has principally agreed to proceed with the rescue excavation, which will be carried out in accordance with relevant regulations.

The Chia-Yi Science Park is a key hub for developing the Great Southern Technology Corridor. Besides providing backend CoWoS (Chip-on-Wafer-on-Substrate) packaging for TSMC’s 2nm process from its Kaohsiung plant, the Chia-Yi facility will further integrate advanced 3D packaging technology, SoIC (System-on-Integrated-Chips), highlighting its strategic importance.

As AI chips continue to evolve, the competition in advanced packaging remains fierce, with many clients eagerly anticipating developments.

TSMC’s advanced packaging capacity is scarce, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. Broadcom, Amazon, and Marvell have also expressed strong interest in using advanced packaging processes.

Per a report from global media outlet Wccftech, NVIDIA’s Rubin GPU is expected to adopt a 4x reticle design and utilize TSMC’s CoWoS-L packaging technology, along with the N3 process. Moreover, NVIDIA will use next-generation HBM4 DRAM to power its Rubin GPU.

Industry sources cited in Commercial Time’s report have indicated that by the end of next year, TSMC’s monthly CoWoS capacity will be increased to 60,000 wafers. With growing orders and a steep learning curve, the annual capacity is expected to surpass 600,000 wafers next year. As the semiconductor industry advances into the Angstrom Era, the gap in TSMC’s advanced packaging capacity will gradually widen. Whether the Chia-Yi plant can be completed by 2026 remains a critical focal point.

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(Photo credit: TSMC)

NVIDIA CEO Jensen Huang delivered a keynote speech at the NTU (National Taiwan University) Sports Center on June 2. As per a report from TechNews, during the speech, he unveiled the new generation Rubin architecture, showcasing NVIDIA’s accelerated rollout of new architectures, which became the highlight of the evening.

While discussing NVIDIA’s next-generation architecture, Huang mentioned the Blackwell Ultra GPU and indicated that it may continue to be upgraded. He then revealed that the next-generation architecture following Blackwell will be the Rubin architecture.

The Rubin GPU will feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, he noted.

The new architecture has been named after American astronomer Vera Rubin, who made significant contributions to our understanding of dark matter in the universe and conducted pioneering work on galaxy rotation rates.

Notably, despite the fact that NVIDIA has just launched the new Blackwell platform, it appears that NVIDIA keeps accelerating its roadmap. According to the latest information announced by Jensen Huang, the Rubin GPU will become part of the R series products and is expected to go into mass production in the fourth quarter of 2025. The Rubin GPU and its corresponding platform are anticipated to be released in 2026, followed by the Ultra version in 2027. NVIDIA also confirmed that the Rubin GPU will use HBM4.

Per a report from global media outlet Wccftech, NVIDIA’s Rubin GPU is expected to adopt a 4x reticle design and utilize TSMC’s CoWoS-L packaging technology, along with the N3 process. Moreover, NVIDIA will use next-generation HBM4 DRAM to power its Rubin GPU.

According to Wccftech, currently, NVIDIA employs the fastest HBM3e in its B100 GPU, and it plans to update these chips with the HBM4 version when HBM4 solutions are produced in large quantities by the end of 2025.

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(Photo credit: NVIDIA)