At the SEMICON Taiwan 2024, Samsung’s Head of Memory Business, Jung Bae Lee, stated that as the industry enters the HBM4 era, collaboration between memory makers, foundries, and customers is becoming increasingly crucial.

Reportedly, Samsung is prepared with turnkey solutions while maintaining flexibility, allowing customers to design their own basedie (foundation die) and not restricting production to Samsung’s foundries.

As per anue, Samsung will actively collaborate with others, with speculation suggesting this may involve outsourcing orders to TSMC.

Citing sources, anue reported that SK hynix has signed a memorandum of understanding with TSMC in response to changes in the HBM4 architecture. TSMC will handle the production of SK hynix’s basedie using its 12nm process.

This move helps SK hynix maintain its leadership while also ensuring a close relationship with NVIDIA.

Jung Bae Lee further noted that in the AI era, memory faces challenges of high performance and low energy consumption, such as increasing I/O counts and faster transmission speeds. One solution is to outsource the basedie to foundries using logic processes, then integrate it with memory through Through-Silicon Via (TSV) technology to create customized HBM.

Lee anticipates that this shift will occur after HBM4, signifying increasingly close collaboration between memory makers, foundries, and customers. With Samsung’s expertise in both memory and foundry services, the company is prepared with turnkey solutions, offering customers end-to-end production services.

Still, Jung Bae Lee emphasized that Samsung’s memory division has also developed an IP solution for basedie, enabling customers to design their own chips. Samsung is committed to providing flexible foundry services, with future collaborations not limited to Samsung’s foundries, and plans to actively partner with others to drive industry transformation.

Reportedly, Samsung is optimistic about the HBM market, projecting it to reach 1.6 billion Gb this year—double the combined figure from 2016 to 2023—highlighting HBM’s explosive growth.

Address the matter, TrendForce further notes that for the HBM4 generation base die, SK hynix plans to use TSMC’s 12nm and 5nm foundry services. Meanwhile, Samsung will employ its own 4nm foundry, and Micron is expected to produce in-house using a planar process. These plans are largely finalized.

For the HBM4e generation, TrendForce anticipates that both Samsung and Micron will be more inclined to outsource the production of their base dies to TSMC. This shift is primarily driven by the need to boost chip performance and support custom designs, making further process miniaturization more critical.

Moreover, the increased integration of CoWoS packaging with HBM further strengthens TSMC’s position as it is the main provider of CoWoS services.

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(Photo credit: TechNews)

As Samsung plans to unveil its next-gen flagship smartphone, Galaxy S25 series, in early 2025, more details regarding the product have surfaced. Months ahead of the launch, Samsung is said to abandon the dual-processor strategy and equip the entire series with Qualcomm’s new Snapdragon 8 Gen 4 processor. The latest rumor, however, may be related to the yield issue in its 1b DRAM intended to be used in the Galaxy S25 series.

According to a report by Korean media outlet ZDNet, the tech giant might be facing difficulties in its cutting-edge mobile DRAM, the 1b DRAM (5^th-generation 10nm-class DRAM). Last month, Samsung Electronics’ Mobile eXperience (MX) Division reportedly raised concerns with the Device Solutions (DS) Division about delays in the delivery of 1b-based LPDDR (low-power DRAM) samples.

Samsung has been developing 1b DRAM for a period of time, as the company is said to begin mass production of the 16Gb 1b DDR5 DRAM in May last year, ZDNet notes. Afterwards, Samsung started to develop the 32Gb 1b DRAM in September, targeting the high-performance computing (HPC) market, the report states.

Meanwhile, it has been working on developing 1b LPDDR products for mobile devices, primarily targeting the Galaxy S25 series.

However, recent issues seem to have disrupted these plans, the report suggests. It notes that while the DS Division was expected to deliver 1b LPDDR samples in various capacities, including 12Gb and 16Gb, to the MX Division by last month, they were unable to provide the necessary quantities due to yield problems.

Industry experts cited by the report indicate that semiconductors generally require a yield rate above 80% to support stable and cost-effective mass production and supply. While the exact yield rate of Samsung’s mobile 1b DRAM hasn’t been revealed, it is likely to fall well below the target, which prompts Samsung’s MX Division to reevaluate the schedule and the DRAM adoption plan, the report suggests.

According to a previous report by TheElec, though concerns have been raised regarding its 1b DRAM manufacturing, being ambitious on its HBM development, Samsung targets to tape out HBM4 by the end of this year, while it intends to adopt the 10nm 6th-generation (1c) DRAM to manufacture the memory chip.

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• [News] Samsung Rumored to Abandon Exynos 2500, Equipping Entire S25 Series with Snapdragon

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Recently, Samsung Electro-Mechanics announced that by 2026, the sales share of its high-end Flip Chip Ball Grid Array (FCBGA) substrates for server and artificial intelligence will exceed 50%.

FCBGA is an integrated circuit (IC) packaging technology，which involves flipping the chip and connecting it to the packaging substrate, then using spherical solder bumps to attach the package to the substrate.

It is mainly used in the packaging of high-density, high-speed, multi-functional large-scale IC chips, offering advantages such as high integration, small size, high performance, and low power consumption.

After a prolonged period of inventory cutting, the balance between semiconductor supply and demand sides has improved, with market demand gradually recovering.

The strong demand in fields such as high-speed network, server, smart driving, and optical module has continuously energized the development of high-multilayer high-speed boards and advanced HDI boards, which in turn is gradually boosting the prosperity of the packaging substrate industry.

As one of the main packaging methods for core electronic components like PC central processing unit, memory, and graphics processor, FCBGA boasts significant market potential in the development of 5G communications, artificial intelligence, virtual reality, and other fields.

Globally, IDM companies such as Micron, Infineon, and NXP have conducted extensive research and development in the FCBGA packaging field, while specialized packaging and testing companies like ASE Group, JCET, and Amkor have also developed various FCBGA technologies.

It is reported that numerous major international semiconductor companies, including Intel, Qualcomm, NVIDIA, AMD, and Samsung, are utilizing FCBGA technology.

Intel is one of the pioneers of FCBGA technology, first applying it to processors in 1997, while Apple is a loyal adopter of FCBGA technology, having used it in its processors from an early stage.

Data indicates that the global FCBGA packaging technology market will continue to grow rapidly in the coming years, with the market size expected to exceed USD 20 billion by 2026.

In face of such a highly potential opportunities, an increasingly more companies are channeling more efforts in developing FCBGA packaging technology, continuously facilitating its innovation and upgrade, and Chinese companies are also a part of this competition.

Currently, main companies engaging in FCBGA packaging substrates business in China include Fastprint, SCC, and FHEC (Forehope-elec), etc, which have disclosed their current progresses referring to FCBGA research and development.

Besides, Strongteam, a real estate company attempting to enter the semiconductor field, has set its sight on the FCBGA sector.

Fastprint disclosed that its low-layer FCBGA packaging substrates are currently in the small-batch delivery stage, with primary applications in the automotive and AI sectors.

SCC stated that it already has the capability of mass producing FCBGA packaging substrates with 16 layers and less, and the capability of sample manufacturing products with more than 16 layers.

The production line validation, sample delivery, and certification processes for various product levels have proceeded smoothly on track. Strongteam is actively transitioning into the semiconductor field and plans to invest in high-end FCBGA IC substrate enterprises.

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(Photo credit: Samsung)

Intel and Japan’s National Institute of Advanced Industrial Science and Technology (AIST), under the Ministry of Economy, Trade and Industry, are reportedly planning to set up an R&D hub in Japan. As per a report from Tom’s Hardware, the new facility is expected to be built within the next 3-5 years, with a total investment projected to reach hundreds of millions of dollars.

According to a report from Nikkei on September 3rd, this facility is said to be putting more focus on developing advanced semiconductor manufacturing equipment and materials, as well as introducing Extreme Ultraviolet (EUV) lithography.

On the other hand, the hub will feature EUV lithography equipment, with AIST overseeing operations and Intel providing expertise in semiconductor manufacturing using EUV equipment.

The report from Nikkei indicates that Rapidus, expected to mass-produce 2nm chips by 2027, will introduce Japan’s first EUV lithography equipment in December 2024. The planned R&D hub, per Nikkei, will become the first research institution in Japan to incorporate such tool. The hub is also considering technical collaboration and talent exchange with U.S. research institutions.

Reportedly, EUV lithography equipment is essential for producing advanced chips below 5nm, but each unit costs over JPY 40 billion, making it difficult for materials and equipment manufacturers to purchase independently.

Therefore, semicondcutor companies may have to be rely on certain research institutions’ EUV equipment overseas to conduct research and product development, such as imec.

The global semiconductor foundry leader, TSMC, established a next-generation semiconductor R&D hub in Ibaraki Prefecture, Japan, in June 2022. Additionally, Samsung Electronics plans to set up a chip R&D center in Yokohama, Japan, by the end of 2024.

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(Photo credit: Intel)

Recently, wafer foundry market has seen various dynamics from related manufacturers.

TSMC is reportedly planning to build its third plant in Japan, while Samsung has delayed the construction of its Pyeongtaek P4/P5 chip plants to 2026, prioritizing the Texas Taylor wafer plant instead.

Meanwhile, SMIC, Huahong Group, and Nexchip have all released their semi-annual reports, showing steady improvements in capacity utilization rates. SMIC expects its 12-inch monthly capacity to increase by around 60,000 wafers in late 2024 compared to the end of last year.

Huahong is accelerating the construction of its new 12-inch production line in Wuxi, which is expected to start production in the first quarter of next year.

According to a survey by TrendForce, strong demand for AI server has driven the total output value of the world’s top ten wafer foundries to increase by 9.6% quarter-on-quarter in the second quarter, reaching USD 32 billion.

TSMC, Samsung, SMIC, Huahong Group, and Nexchip ranked first, second, third, sixth, and tenth, respectively, among the world’s top ten wafer foundries.

• TSMC Plans to Build the Third Plant in Japan After 2030

J.W. Kuo, head of Taiwan’s economic department, recently stated in an interview that TSMC plans to build its third plant in Japan to produce advanced semiconductors, with the construction expected to commence after 2030.

TSMC’s first plant in Kumamoto, Japan, (Kumamoto P1) is expected to start mass production in 4Q24 (October-December), using 28/22nm and 16/12nm process technologies, with a monthly capacity of 55,000 wafers.

The second planned plant, also located in Kumamoto, is scheduled to commence construction at the end of 2024, with operations starting in late 2027, focusing on 6/7nm processes.

The combined monthly capacity of TSMC’s Kumamoto P1 and P2 is expected to exceed 100,000 wafers. TSMC Chairman C.C.Wei mentioned in June that after the first and second plants are operational, TSMC may consider building a third plant in Kumamoto if the local residents agree.

• Samsung Delays the Construction of Pyeongtaek P4/P5 Plants to 2026, Prioritizing Texas Taylor Plant

Per global media reports on September 2, Samsung has postponed the construction of the second and fourth phase production lines of the Pyeongtaek P4 and P5 plants to 2026. Samsung is currently focusing on building a wafer plant in Taylor, Texas.

It is reported that Samsung did not conduct the necessary financial review for the Pyeongtaek P5 plant by the end of July 2024, leading to delays in the construction plans for both P5 and P4 plants.

However, the first-phase production line of P4 plant, which produces NAND Flash, is expected to start production soon. The third-phase production line is currently under construction, with plans to install power equipment after the Mid-Autumn Festival.

The original plan for P4 plant was to first build a memory production line (Phase 1), then a wafer foundry line (Phase 2), followed by additional memory and wafer foundry lines (Phases 3 and 4) to complete P4 plant.

However, it is reported that the wafer foundry business at this production line failed to meet expectations, prompting Samsung to prioritize the construction of memory production lines.

The sources cited by DRAMExchange revealed that the product lineup for the P4 Phase 2 production line is expected to be finalized between January and February 2025.

The Taylor plant began construction in the first half of 2022 and is expected to put into operation in 2026. The project’s investment scale is approximately USD 17 billion, with wafer manufacturing originally planned for the 4nm node.

However, industry news from June 2024 indicates that Samsung has added 2nm advanced process technology to meet the demand driven by the AI wave.

In April 2024, Samsung signed an agreement with the U.S. Department of Commerce to receive USD 6.4 billion in subsidies under the CHIPS Act.

• SMIC’s Revenue Grows by 23.2% Year-on-Year

Recently, SMIC released its half-yearly financial results, showing that the company achieved a revenue of CNY 26.269 billion, a year-on-year increase of 23.2%.

The net profit attributable to the parent company was CNY 1.646 billion, a year-on-year decrease of 45.1%, and the net profit after deducting non-recurring gains and losses was CNY 1.288 billion, a year-on-year decrease of 27%.

In terms of capacity utilization, SMIC’s 8-inch utilization rate has rebounded. The company stated that its 12-inch capacity has been near full load in recent quarters, with additional effective capacity added in the first half of this year, and the new capacity has been rapidly put into production.

The company’s overall capacity utilization rate increased to 85%, up 4 percentage points from the previous quarter.

These financial results highlight two key indicators that send an important signal to the market. Although SMIC’s profits fell short of expectations, its revenue continued to rise, reflecting signs of recovery in downstream markets.

Beyond the recovery in revenue, the increase in capacity utilization is a major highlight of the report.

Data indicates that the main drivers of SMIC’s revenue turnaround were the smartphone and consumer electronics business, further demonstrating signs of recovery in the semiconductor market.

As to wafer revenue by size, demand for 8-inch wafers has rebounded, with the revenue share increasing to 26%, up 2 percentage points from the previous quarter, while the revenue share for 12-inch wafer is 74%.

Regarding capacity expansion, SMIC expects its 12-inch monthly capacity to increase by around 60,000 wafers by the end of this year compared to the end of last year. SMIC provided guidance for the third quarter, projecting a revenue growth of 13% to 15% quarter-on-quarter, with a gross margin between 18% and 20%.

• Huahong’s Capacity Utilization Rate Exceeded 100% in Q2

Huahong achieved operating income of around CNY 6.732 billion in the first half of the year, a year-on-year decrease of 23.88%. The net profit attributable to shareholders was CNY 265 million, a year-on-year decrease of 83.33%.

It expects third-quarter sales revenue of CNY 500 million to 520 million, with a gross margin between 10% and 12%.

In terms of capacity utilization, Huahong reported that the company’s 8-inch capacity utilization rate surpassed 100% in the second quarter, with the 12-inch capacity utilization rate closed to full capacity.

The overall capacity utilization rate was 97.9%, a significant improvement from 91.7% in the first quarter, but still below the 102.7% capacity utilization rate in the second quarter of last year, indicating that Huahong has not yet returned to its peak level.

On product mix, Huahong’s major revenue contributors are discrete device and embedded non-volatile memory. In the second quarter of this year, the combined revenue share of these two segments was 60.5%.

Regarding production, the company is accelerating the construction of its new 12-inch production line in Wuxi.

In August, Huahong announced that the first phase of Wuxi base currently has a capacity of 94,500 wafers per month, with nearly all process platforms steadily scaling up production.

The second phase of Wuxi, after about a year of construction, is now 80% of completion, with the first equipment installation scheduled for the end of August. The production line is expected to be completed by the end of the year, with capacity to be released starting in the first quarter of next year.

• Nexchip Turned Profitable Compared to the Same Period of Last Year

Nexchip achieved a revenue of CNY 4.398 billion, a year-on-year increase of 48.09%, and a net profit attributable to the parent company of CNY 187 million, turning losses into gains year on year. The company’s gross margin was 24.43%.

Nexchip mainly engages in 12-inch wafer foundry services, providing wafer foundry services for DDIC and other process platforms.

In 1H24, the revenue share from CIS has significantly increased, making it the company’s second-largest product segment, with CIS capacity running at full load.

The company’s current wafer foundry capacity is 115,000 wafers per month, and it plans to expand capacity by 30,000 to 50,000 wafers per month in 2024, focusing on 55nm and 40nm nodes, with a primary focus on advanced CIS.

From a quarter-on-quarter perspective, the semi-annual reports of the three major foundries, SMIC, Huahong, and Nexchip, indicate a gradual upturn in business performance and steady improvement in capacity utilization rate.

Industry sources cited by DRAMExchange suggested that this signals an accelerated speed of recovery in the semiconductor market, and the second half of the year may see more positive surprises.

Read more

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(Photo credit: TSMC)